JPS5793731A - Logical level conversion circuit - Google Patents
Logical level conversion circuitInfo
- Publication number
- JPS5793731A JPS5793731A JP55170063A JP17006380A JPS5793731A JP S5793731 A JPS5793731 A JP S5793731A JP 55170063 A JP55170063 A JP 55170063A JP 17006380 A JP17006380 A JP 17006380A JP S5793731 A JPS5793731 A JP S5793731A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- gate
- source
- logical level
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To extend the amplitude of output and to reduce the fluctuations in output level, by providing a circuit consisting of 4 sets of MOSFETs between the 1st and the 2nd inverters of a logical level conversion circuit. CONSTITUTION:A positive logical level signal Vin is inputted to the gate of an MOSFETM5 and the drain is grounded. The drain of an MOSFETM4 is connected to the source of an FETM3, the source is connected to a negative power supply and the gate and the drain are short-circuited. The drain of an MOSFETM6 is connected to the source of an FETM5, the source is to the negative power supply, the gate is to the gate of the FETM4 respectively and the drain is connected to the input of the 2nd inverter. The amplitude of output can be extended by inserting the circuit like this between the 1st and the 2nd inverters, and the fluctuations of the threshold voltage can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170063A JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170063A JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5793731A true JPS5793731A (en) | 1982-06-10 |
JPH0245377B2 JPH0245377B2 (en) | 1990-10-09 |
Family
ID=15897936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55170063A Granted JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5793731A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553051A (en) * | 1983-07-18 | 1985-11-12 | Texas Instruments Incorporated | PMOS Input buffer compatible with logic inputs from an NMOS microprocessor |
EP0220833A2 (en) * | 1985-09-24 | 1987-05-06 | Kabushiki Kaisha Toshiba | Level conversion circuit |
-
1980
- 1980-12-02 JP JP55170063A patent/JPS5793731A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553051A (en) * | 1983-07-18 | 1985-11-12 | Texas Instruments Incorporated | PMOS Input buffer compatible with logic inputs from an NMOS microprocessor |
EP0220833A2 (en) * | 1985-09-24 | 1987-05-06 | Kabushiki Kaisha Toshiba | Level conversion circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0245377B2 (en) | 1990-10-09 |
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