JPS578850A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS578850A JPS578850A JP8424780A JP8424780A JPS578850A JP S578850 A JPS578850 A JP S578850A JP 8424780 A JP8424780 A JP 8424780A JP 8424780 A JP8424780 A JP 8424780A JP S578850 A JPS578850 A JP S578850A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- address
- storage device
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To perform reading and writing operation in a storage device efficiently by providing a circuit which controls the operation of the storage device as well as a means of converting logical addresses into physical addresses in the storage device. CONSTITUTION:When address conversion is disabled, an address conversion specifying signal CPC from a CPU1 is O and the output signal of a NAND circuit 12 is 1, so that selector circuits 6 and 9 select signals MBA and MNS respectively. A logical address signal CPA is therefore inputted as a physical address signal MMA to a data storage module 13, as it is, without being address-converted. A memory start circuit 7 selects a start signal MMS by the circuit 9 and sends it as a timing start signal MTS to drive a timing generating circuit 14. When the address conversion is possible, the signal CPC is 1 and the output signal of the circuit 12 is O. Consequently, the circuit 6 selects an address-converted address signal ATMA, the output of an address conversion memory 5, and the circuit 9 selects the delayed start signal MTS, the output of a delay circuit 10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8424780A JPS578850A (en) | 1980-06-20 | 1980-06-20 | Storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8424780A JPS578850A (en) | 1980-06-20 | 1980-06-20 | Storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS578850A true JPS578850A (en) | 1982-01-18 |
Family
ID=13825128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8424780A Pending JPS578850A (en) | 1980-06-20 | 1980-06-20 | Storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS578850A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4676988A (en) * | 1984-03-19 | 1987-06-30 | General Mills, Inc. | Low-acid juice-milk beverages, juice and milk components therefor and methods of preparation |
-
1980
- 1980-06-20 JP JP8424780A patent/JPS578850A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4676988A (en) * | 1984-03-19 | 1987-06-30 | General Mills, Inc. | Low-acid juice-milk beverages, juice and milk components therefor and methods of preparation |
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