JPS5775346A - Input/output device - Google Patents

Input/output device

Info

Publication number
JPS5775346A
JPS5775346A JP55150990A JP15099080A JPS5775346A JP S5775346 A JPS5775346 A JP S5775346A JP 55150990 A JP55150990 A JP 55150990A JP 15099080 A JP15099080 A JP 15099080A JP S5775346 A JPS5775346 A JP S5775346A
Authority
JP
Japan
Prior art keywords
shift
constitution
phase
series data
shift clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55150990A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6129026B2 (enrdf_load_html_response
Inventor
Masashi Tominaga
Munehiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55150990A priority Critical patent/JPS5775346A/ja
Publication of JPS5775346A publication Critical patent/JPS5775346A/ja
Publication of JPS6129026B2 publication Critical patent/JPS6129026B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
JP55150990A 1980-10-28 1980-10-28 Input/output device Granted JPS5775346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55150990A JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55150990A JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Publications (2)

Publication Number Publication Date
JPS5775346A true JPS5775346A (en) 1982-05-11
JPS6129026B2 JPS6129026B2 (enrdf_load_html_response) 1986-07-03

Family

ID=15508867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55150990A Granted JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Country Status (1)

Country Link
JP (1) JPS5775346A (enrdf_load_html_response)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113398A (ja) * 1983-11-22 1985-06-19 Seiko Epson Corp 半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113398A (ja) * 1983-11-22 1985-06-19 Seiko Epson Corp 半導体集積回路

Also Published As

Publication number Publication date
JPS6129026B2 (enrdf_load_html_response) 1986-07-03

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