JPS5775346A - Input/output device - Google Patents

Input/output device

Info

Publication number
JPS5775346A
JPS5775346A JP55150990A JP15099080A JPS5775346A JP S5775346 A JPS5775346 A JP S5775346A JP 55150990 A JP55150990 A JP 55150990A JP 15099080 A JP15099080 A JP 15099080A JP S5775346 A JPS5775346 A JP S5775346A
Authority
JP
Japan
Prior art keywords
shift
constitution
phase
series data
shift clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55150990A
Other languages
Japanese (ja)
Other versions
JPS6129026B2 (en
Inventor
Masashi Tominaga
Munehiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55150990A priority Critical patent/JPS5775346A/en
Publication of JPS5775346A publication Critical patent/JPS5775346A/en
Publication of JPS6129026B2 publication Critical patent/JPS6129026B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Abstract

PURPOSE:To increase the degree of feedom for the constitution of a system that performs a mutual transmission/reception of a series data, by providing a means that controls the phase of the shift clock pulse to be supplied to a shift register via a logic gate circuit. CONSTITUTION:Two shift registers SA and SB perform a mutual transmission/ recepton of a series data. A shift clock circuit 11 supplies the shift clock pulse phi to the registers SA and SB via a logic gate circuit 15. In addition, a means is provided to control the phase of the pulse phi via the cicuit 15. For instance, an input/ output interface is constituted as shown in the diagram between a system A of a microcomputer, etc. and a system B of a magnetic card reader, etc. Then a shift mode flip-flop 16 is added as a means to control the phase of the pulse phi. As a result, the transmission/reception timing of the series data can be set in accordance with each system to increase the degree of freedom for the constitution of a system.
JP55150990A 1980-10-28 1980-10-28 Input/output device Granted JPS5775346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55150990A JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55150990A JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Publications (2)

Publication Number Publication Date
JPS5775346A true JPS5775346A (en) 1982-05-11
JPS6129026B2 JPS6129026B2 (en) 1986-07-03

Family

ID=15508867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55150990A Granted JPS5775346A (en) 1980-10-28 1980-10-28 Input/output device

Country Status (1)

Country Link
JP (1) JPS5775346A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113398A (en) * 1983-11-22 1985-06-19 Seiko Epson Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60113398A (en) * 1983-11-22 1985-06-19 Seiko Epson Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6129026B2 (en) 1986-07-03

Similar Documents

Publication Publication Date Title
EP0126163A4 (en) Controller with status display unit.
JPS6418312A (en) Four-state input/output control circuit
EP0295409A3 (en) Programmable skew-tolerant array processor architecture
JPS5647125A (en) Delay circuit
JPS5775346A (en) Input/output device
JPS5338373A (en) Ic for watch
JPS54154964A (en) Programable counter
JPS558166A (en) Data transmission system
JPS57158095A (en) Shift register circuit
JPS5799062A (en) Reception circuit for data transmission
JPS54143031A (en) Driving control system of shift register circuit
GB962095A (en) Improvements in or relating to electronic data-manipulating apparatus
JPS5680931A (en) Frequency dividing circuit
JPS5534518A (en) Lsi parameter setting system
JPS6419403A (en) Process input device
JPS53121532A (en) 1-bit delay type full adder
JPS5496311A (en) Data serial transmission system
JPS53135677A (en) Electronic watch
FR2391508A1 (en) Time counter for electronic calculator - has logic circuit which gives control of set combination of time and number previously introduced into calculator
JPS57158096A (en) Shift register
JPS55145462A (en) Reproducing circuit of transmission data
JPS55112042A (en) 1/3-divider circuit
JPS57147703A (en) Input and output controller
JPS5781760A (en) Highway test device
JPS5750035A (en) Generation device for constant time interruption signal