JPS5768987A - Memory read-in system for signal reception - Google Patents

Memory read-in system for signal reception

Info

Publication number
JPS5768987A
JPS5768987A JP14547480A JP14547480A JPS5768987A JP S5768987 A JPS5768987 A JP S5768987A JP 14547480 A JP14547480 A JP 14547480A JP 14547480 A JP14547480 A JP 14547480A JP S5768987 A JPS5768987 A JP S5768987A
Authority
JP
Japan
Prior art keywords
signal
bit
inputted
register
control signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14547480A
Other languages
English (en)
Japanese (ja)
Other versions
JPS634397B2 (enExample
Inventor
Hiroshi Miyake
Takashi Nara
Kenzo Aoki
Yasutsugu Nagahama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14547480A priority Critical patent/JPS5768987A/ja
Publication of JPS5768987A publication Critical patent/JPS5768987A/ja
Publication of JPS634397B2 publication Critical patent/JPS634397B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP14547480A 1980-10-17 1980-10-17 Memory read-in system for signal reception Granted JPS5768987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14547480A JPS5768987A (en) 1980-10-17 1980-10-17 Memory read-in system for signal reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14547480A JPS5768987A (en) 1980-10-17 1980-10-17 Memory read-in system for signal reception

Publications (2)

Publication Number Publication Date
JPS5768987A true JPS5768987A (en) 1982-04-27
JPS634397B2 JPS634397B2 (enExample) 1988-01-28

Family

ID=15386078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14547480A Granted JPS5768987A (en) 1980-10-17 1980-10-17 Memory read-in system for signal reception

Country Status (1)

Country Link
JP (1) JPS5768987A (enExample)

Also Published As

Publication number Publication date
JPS634397B2 (enExample) 1988-01-28

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