JPS5756969A - High withstand voltage type semiconductor device - Google Patents
High withstand voltage type semiconductor deviceInfo
- Publication number
- JPS5756969A JPS5756969A JP13164080A JP13164080A JPS5756969A JP S5756969 A JPS5756969 A JP S5756969A JP 13164080 A JP13164080 A JP 13164080A JP 13164080 A JP13164080 A JP 13164080A JP S5756969 A JPS5756969 A JP S5756969A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- withstand voltage
- bevelled
- high density
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000005452 bending Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Abstract
PURPOSE:To increase the withstand voltage of a semiconductor device without deteriorating te characteristics of the device in which the junction surface is bevelled at the end face of an exposed substrate by forming the equal conductive type high density layer in a region extending at the depletion layer of the bevelled part, thereby reducing the bending of the depletion layer. CONSTITUTION:A high density collector layer 3, a base layer 2 and an emitter layer 4 are formed, for example, on an n type high resistance wafer 10 by diffusing them from both main surfaces, as a transistor structure having high resistance collector region 1. Electrodes 4-6 are formed on both main surfaces, the side surface of the wafer is positively bevelled, thereby increasing its withstand voltage. The deflected layer of the treated surface is etched and removed, n type impurity ions are injected in suitably amount at an adequate distance from the junction end 9a to the high resistance collector region 1 of the vebelled surface 10a, thereby forming a high density layer 11. In this manner, the shape 12a of the depletion layer of the collector side at the reverse bias time can be formed with less bending than the case that the injected layer 11 is not formed (as designated by chain line), and high withstand voltage can be formed without inreasing the thickness of the substrate 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13164080A JPS5756969A (en) | 1980-09-24 | 1980-09-24 | High withstand voltage type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13164080A JPS5756969A (en) | 1980-09-24 | 1980-09-24 | High withstand voltage type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5756969A true JPS5756969A (en) | 1982-04-05 |
Family
ID=15062774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13164080A Pending JPS5756969A (en) | 1980-09-24 | 1980-09-24 | High withstand voltage type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5756969A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6701973B2 (en) | 2001-02-23 | 2004-03-09 | Toyo Jidoki Co., Ltd. | Solid matter loading method and a solid matter loading guide device used in a continuous conveying type bag-filling packaging machine |
-
1980
- 1980-09-24 JP JP13164080A patent/JPS5756969A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6701973B2 (en) | 2001-02-23 | 2004-03-09 | Toyo Jidoki Co., Ltd. | Solid matter loading method and a solid matter loading guide device used in a continuous conveying type bag-filling packaging machine |
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