JPS54148486A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54148486A
JPS54148486A JP5668878A JP5668878A JPS54148486A JP S54148486 A JPS54148486 A JP S54148486A JP 5668878 A JP5668878 A JP 5668878A JP 5668878 A JP5668878 A JP 5668878A JP S54148486 A JPS54148486 A JP S54148486A
Authority
JP
Japan
Prior art keywords
region
layer
type
semiconductor layer
inversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5668878A
Other languages
Japanese (ja)
Inventor
Mitsusuke Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5668878A priority Critical patent/JPS54148486A/en
Publication of JPS54148486A publication Critical patent/JPS54148486A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase the dielectric strength only with no increment of the saturation value by diffusing the impurities featuring the opposite conducting performance to the semiconductor layer onto the surface of the semiconductor layer which is to become the collector in such amount as not to cause the inversion in order to lower the impurity density on the surface of the semiconductor layer.
CONSTITUTION: N--type layer 2 is grown on N+-type semiconductor substrate 1, and P-type base region 3 is formed by diffusion on layer 2 with N+-type emitter region 4 provided within region 3. Then N+-type channel stopper region 5 is formed by diffusion within layer 2 across region 3 and also holding region 3 between, and Al electrode 7 is attached to region 3 and 4 each. After this, the P-tupe impurities are diffused on exposed surface A of layer 2 including region 5 and in such amount as not cause the inversion into P-type with N---type layer 8 provided, and then the entire surface is covered with SiO2 film 6. As a result, the depletion layer caused when the backward bias is applied between the collector and the base extends completely up to stopper 5 to increase BVCEO. And Vcmsat is never increased since it is determined by region B existing between substrate 1 and region 3.
COPYRIGHT: (C)1979,JPO&Japio
JP5668878A 1978-05-15 1978-05-15 Semiconductor device Pending JPS54148486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5668878A JPS54148486A (en) 1978-05-15 1978-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5668878A JPS54148486A (en) 1978-05-15 1978-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54148486A true JPS54148486A (en) 1979-11-20

Family

ID=13034373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5668878A Pending JPS54148486A (en) 1978-05-15 1978-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54148486A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834963A (en) * 1981-08-26 1983-03-01 Nec Corp Semiconductor device
JPS5879775A (en) * 1981-11-07 1983-05-13 Mitsubishi Electric Corp Planar type diode
JPS6219757U (en) * 1985-07-19 1987-02-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834963A (en) * 1981-08-26 1983-03-01 Nec Corp Semiconductor device
JPS5879775A (en) * 1981-11-07 1983-05-13 Mitsubishi Electric Corp Planar type diode
JPS6219757U (en) * 1985-07-19 1987-02-05

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