JPS5879775A - Planar type diode - Google Patents

Planar type diode

Info

Publication number
JPS5879775A
JPS5879775A JP17861681A JP17861681A JPS5879775A JP S5879775 A JPS5879775 A JP S5879775A JP 17861681 A JP17861681 A JP 17861681A JP 17861681 A JP17861681 A JP 17861681A JP S5879775 A JPS5879775 A JP S5879775A
Authority
JP
Japan
Prior art keywords
layer
type
substrate
semiconductor
distance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17861681A
Other languages
Japanese (ja)
Inventor
Ideo Maeyama
前山 出男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17861681A priority Critical patent/JPS5879775A/en
Publication of JPS5879775A publication Critical patent/JPS5879775A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve electrostatic breakdown resistance by making a distance between the first semiconductor layer and the second semiconductor layer surrounding the first semiconductor layer larger than thickness just under the first semiconductor layer of a substrate. CONSTITUTION:Carriers reach an n<++> type Si layer 7 before a depletion layer (a) extending into the substrate 1 from a p type Si layer 2 reaches an n<++> type annular Si layer 3 from the layer 2 when reverse voltage is applied between an anode 6 and a cathode 8 because the distance la between the Si layers 2 and 3 is made larger than the thickness t between the layer 2 of the i type Si substrate 1 and the layer 7, and the generation of electrostatic breakdown between the layer 2 and the layer 3 can be prevented.

Description

【発明の詳細な説明】 この発明は高抵抗率管有し真性半導体として働く半導体
基板管用いて構成されたpinJ造のプレーす形ダイオ
ードに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pinJ square diode constructed using a semiconductor substrate tube having a high resistivity tube and acting as an intrinsic semiconductor.

あることを利用し刃、通信機、テレビジョン受像機など
に広く使用されている。
Taking advantage of this fact, it is widely used in blades, communication equipment, television receivers, etc.

第1図社従来のp1n構造のブレーナ形ダイオードの一
例を示す断面図である。
FIG. 1 is a sectional view showing an example of a conventional Brehner diode having a p1n structure.

図において、+lid li!00ON5000Ω−a
m程度の抵抗率を有し真性半導体とし働くn形シリコン
(81)基板(以下「1形s1基板」と呼ぶ) 、(!
lは1形81基板+11の第1の主面部の一部分にp形
不純物を導入して形成されたpy#81層、1B1Fi
i形81基板(11の第1の主面部Kp形81層(2)
との関に図示距離lをおいてp形81層(り會取囲むよ
うにn形不純物を高濃度に導入して形成された環状のn
++形B形層1層4)はp形81層(21、n++形8
形層1層)および1形s1基板(1)の表面上にわたっ
て形成された酸化ケイ素(810z) II、(Ilは
p形81層(り上の8102展(4)K設けられ次コン
タクトホール、(6)はコンタクトホール(6)を通し
てp形Bi層(!)とオーンツク接触するように形成さ
れた陽極、(7)は1形81基板(1)の第2の主面部
にn形不純物を高濃度に導入して形成されたn++形s
形層1層8)はn++形8形層1層)の表面上にこれと
オーミック接触するように形成された一極である。
In the figure, +lid li! 00ON5000Ω-a
An n-type silicon (81) substrate (hereinafter referred to as "1-type S1 substrate") that has a resistivity of about m and acts as an intrinsic semiconductor, (!
l is a py#81 layer formed by introducing p-type impurities into a part of the first main surface of the 1-type 81 substrate + 11, 1B1Fi
I-type 81 substrate (11 first main surface part Kp-type 81 layer (2)
An annular n-type layer is formed by introducing n-type impurities at a high concentration to surround 81 p-type layers at a distance l as shown in the figure.
++ type B type layer 1 layer 4) is p type 81 layer (21, n++ type 8
silicon oxide (810z) formed over the surface of the p-type 81 layer (1 layer) and the 1-type S1 substrate (1); (6) is an anode formed to be in direct contact with the p-type Bi layer (!) through the contact hole (6), and (7) is an anode formed on the second main surface of the 1-type 81 substrate (1) with n-type impurities. n++ type s formed by introducing high concentration
The type layer 1 layer 8) is a single pole formed on the surface of the n++ type 8 type layer 1) so as to be in ohmic contact therewith.

ところで、陽極(6)と陰極(8)との間に逆方向電圧
が印加された場合には、p形81層(2)から1形81
基板(1)内へ伸びる一点鎖線で示す空乏層(イ)によ
って、1形81基板+11の8102膜(4)との界面
部においてリーク電流が発生しやすく、シかも空乏層(
づが1形日1基板+11の端面に到達するとリーク電流
が不安定になるので、この従来例でハ、n”v 81層
(Biを設けて空乏層0)が1形s1基板(1)の端面
に到達するのを防止し、リーク電流を小さくする丸めV
Ln++形81層(3)とp形81層(2)との間の図
示距離lが可能な限り小さくなるように設定されていた
By the way, when a reverse voltage is applied between the anode (6) and the cathode (8), the p-type 81 layer (2)
Due to the depletion layer (A) shown by the dashed line extending into the substrate (1), leakage current is likely to occur at the interface between the 1 type 81 substrate + 11 and the 8102 film (4).
When the leakage current reaches the end face of the 1-type 1-type substrate + 11, the leakage current becomes unstable, so in this conventional example, the n"v 81 layer (Bi is provided and the depletion layer is 0) is 1-type S1 substrate (1). The rounded V prevents the leakage current from reaching the end face and reduces the leakage current.
The illustrated distance l between the Ln++ type 81 layer (3) and the p type 81 layer (2) was set to be as small as possible.

この距離lが1形81基板(1)のp形81層(2)と
n 形81層(7)との間の厚さく図示t)より小さく
なると、空乏層(イ)がp形Si#(!lからn 形日
1層(7)に到達する以前にn++形8形層1層+31
到達し、との空乏層(イ)が真先に到達するn++形s
形層1層+11面部の不純物濃度が高いので、空乏層(
イ)がn++形8形層1層+31達すると直ちKp形8
1層(2)とn++形8形層1層)との間に静電破壊が
生じ、この静電破11によってこのプレーナ形ダイオー
ドの静電破壊耐量が低下する。ところが、リーク電流が
小さいことより静電破壊耐量の大きいことが会費な場合
がある。例えば、このプレーナ形ダイオードを通信機な
どのアンテナとの接続部に用いた場合には、通常p形s
t Me 121とn++形B形層1層)との間に印加
される逆方向電圧扛さほど大きなものではないが、アン
テナがオープン状態になるなどのトラブルが発生すると
、このときの逆方向電圧が通常のと自の数十倍にも達す
ることがあるので、このときの逆方向電圧によるB1層
(りおよび(3)間の静電破壊によって、このプレーナ
形ダイオード自体の破壊にとどまらず、このプレーナ形
ダイオードを使用した通信機などの故障をも引色起す可
能性があり、このプレーナ形ダイオードの静電破壊耐量
をも大きくする必要がある。
When this distance l becomes smaller than the thickness t) between the p-type 81 layer (2) and the n-type 81 layer (7) of the 1-type 81 substrate (1), the depletion layer (a) becomes p-type Si# (!l to n Before reaching the 1st layer (7), the n++ 8th layer 1st layer + 31
and the depletion layer (a) of and reaches the n++ type s directly
Since the impurity concentration in the 1st layer + 11th surface area is high, the depletion layer (
A) immediately reaches the n++ type 8 layer 1 layer + 31, the Kp type 8
Electrostatic breakdown occurs between the first layer (2) and the n++ type 8 type layer (first layer), and this electrostatic breakdown 11 reduces the electrostatic breakdown resistance of this planar diode. However, there are cases where a high electrostatic breakdown resistance is more important than a low leakage current. For example, when this planar diode is used in a connection with an antenna of a communication device, it is usually a p-type s
The reverse voltage applied between tMe 121 and the n++ type B layer (1 layer) is not very large, but if a problem such as the antenna becoming open, the reverse voltage at this time will increase. The electrostatic damage caused by the reverse voltage at this time between the B1 layer (and (3)) not only destroys the planar diode itself, but also damages the planar diode itself. This may also cause discoloration of communication devices that use planar diodes, so it is necessary to increase the electrostatic breakdown resistance of these planar diodes.

この発明社、上述の点Kil!みてなされたもので、真
性半導体として働く第1伝導形の半導体基板の一方の主
面部の一部分に形成され九第゛士伝導形の第1の半導体
層とこれを取囲むように形成された高不純物浸度の第命
伝導形の第2の半導体層との間の距離を、上記半導体基
板の上記第i伝導形の第1の半導体層直下の厚さよ抄大
きくすることによって、静電破壊耐量を改善したプレー
ナ形ダイオードを提供することを目的とする。
This invention company, above-mentioned point Kill! A first semiconductor layer of a ninth conductivity type is formed on a part of one main surface of a semiconductor substrate of a first conductivity type that acts as an intrinsic semiconductor, and a high-temperature layer is formed surrounding it. By increasing the distance between the second semiconductor layer of the impurity conductivity type and the second semiconductor layer of the i-th conductivity type of the semiconductor substrate, the electrostatic breakdown resistance can be increased. The purpose of the present invention is to provide a planar diode with improved characteristics.

第2図はこの発明の一実施例のpin構造のプレー1形
ダイオードを示す断藺図である。
FIG. 2 is a cross-section diagram showing a pin-type play type diode according to an embodiment of the present invention.

図において、第1図に示し九従来例と同一符号は同等部
分を示し、その説明は省略する。
In the figure, the same reference numerals as in the conventional example shown in FIG. 1 indicate the same parts, and the explanation thereof will be omitted.

この実施例の構成は、p形81層(2)と環状のn++
形8形層1層)との間の図示距離/aを1形s1基板(
1)のp形81層(2)とn” B ill (’71
との間の厚さく図示t)より大きくした以外は第1図に
示した従来例の構成と同様である。
The structure of this example is a p-type 81 layer (2) and an annular n++
The illustrated distance/a between the type 8 type s1 substrate (1 layer)
1) p-type 81 layer (2) and n”Bill ('71
The structure is the same as that of the conventional example shown in FIG. 1, except that the thickness between t) and t) is made larger than that shown in the figure.

この実施例のプレーナ形ダイオードでは、81層(2)
および(3)間の距離11を1形81基板i11ノst
層(!)および(7)間の厚さtより大急〈シたので、
陽極C・)と陰極(8)との間に逆方向電圧が印加され
たと自に、p形81層(りから1形81基板(1)内へ
伸びる空乏層(4)がp形81層(りから環状のn++
形8形層1層)K到達する以前にn++形8形層1層K
到達し、p形81層(りとn0形81層(3)との間に
静電破壊が生ずるのを防止することができる。、しかも
、空乏層(そのn++形8形層1層)への到達によって
p形81層(!1とn“形8i層(7)との間に静電破
壊が生ずるかどうかa、n”+形81層け)の不純物濃
度で決定される。このn+”f4 $ i層(71には
その陰極(8)側の表面からのn形不純物の導入によっ
て1形81基板(1)側に向って不純物濃度が小さくな
る不純物濃度勾配があり、この不純物濃度勾配によって
空乏層(イ)がn++形B形層1層)に到達し、ても、
p形81層(2)とn 形81層(7)との間に静電破
壊が生じにくいので、静電破壊耐量を向上させることが
できる。
In the planar diode of this example, 81 layers (2)
and (3) the distance between 11 and 1 type 81 board i11 nost
Since the thickness between layer (!) and (7) is much steeper than t,
When a reverse voltage is applied between the anode C. (from ri to cyclic n++
(1 layer of type 8 layer) Before reaching K, 1 layer of n++ type 8 layer K
It is possible to prevent electrostatic damage from occurring between the p-type 81 layer (3) and the n0-type 81 layer (3).Moreover, it is possible to prevent electrostatic discharge from occurring between the p-type 81 layer and the n0-type 81 layer (3). Whether or not electrostatic breakdown occurs between the p-type 81 layer (!1 and the n" type 8i layer (7) is determined by the impurity concentration of the p-type 81 layer (a, n"+ type 81 layer) due to the arrival of this n+ "f4 $ The i layer (71) has an impurity concentration gradient in which the impurity concentration decreases toward the 1 type 81 substrate (1) side due to the introduction of n-type impurities from the surface on the cathode (8) side, and this impurity concentration Due to the gradient, the depletion layer (a) reaches the n++ type B type layer (1 layer),
Since electrostatic damage is less likely to occur between the p-type 81 layer (2) and the n-type 81 layer (7), the electrostatic damage resistance can be improved.

なお、この実施例において、p影領域をn影領域にし、
n影領域をp影領域にした場合でも、この実施例と同様
の効果のあることは言うまでもないO 以上、説明したように、この発明のプレーナ形ダイオー
ドでは、真性半導体として働く第1伝導形の半導体基板
の第1の主面部の一部分に形成された第り 会伝導形の第1の半導体層と、この第1の半導体層との
間に所定距離をおいて上記第1の半導体層を取囲んで環
状に形成され高不純物濃度を有する部署伝導形の第2の
半導体層と、上記半導体基板の第2の主面部に形成され
高不純物濃度を有する謔金伝導形のw、3の半導体層と
を備えたものにおいて、上記第1および第2の半導体層
間の上記所定距離を上記半導体基板の上記第1および第
3の半導体層間の厚さより大きくしたので、上記第1お
よびjlsの半導体層間に逆方向電圧が印加されたとき
に、上記第1の半導体層から上記真性中導体基板内に伸
びる空乏層が上記第2の半導体層に到達する以前に上記
第3の半導体層に到達し、上記第1および纂2の半導体
層間に静電破壊が生ずるのを防止することが可能と表り
、静電破壊耐量を向上させることができる。
In addition, in this example, the p shadow area is changed to the n shadow area,
It goes without saying that even if the n-shade region is changed to a p-shade region, the same effect as in this embodiment can be obtained. The first semiconductor layer is removed with a predetermined distance between the first semiconductor layer of the first conductivity type formed on a portion of the first main surface of the semiconductor substrate and the first semiconductor layer. a second conduction type semiconductor layer surrounded by a ring and having a high impurity concentration; and a conduction conduction type semiconductor layer W, 3 formed on the second main surface of the semiconductor substrate and having a high impurity concentration. Since the predetermined distance between the first and second semiconductor layers is made larger than the thickness between the first and third semiconductor layers of the semiconductor substrate, there is a distance between the first and jls semiconductor layers. When a reverse voltage is applied, the depletion layer extending from the first semiconductor layer into the intrinsic medium conductor substrate reaches the third semiconductor layer before reaching the second semiconductor layer, and It appears that it is possible to prevent electrostatic damage from occurring between the first and second semiconductor layers, and the electrostatic damage resistance can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のブレーナ形ダイオードの一例を示す断面
図、第2図はこの発明の一実施例のブレーナ形ダイオー
ドを示す断面図である。 図において、(1)は1形81基板(第1伝導形の半導
体基板) 、(21はp形81MI(第士伝導形の第1
のヱ 半導体層) 、+31はn−形81層(第曾伝導形の第
2の半導体層) 、(71はn 形8i層(all伝導
形の第5の半導体層)である。 なお、図中同一符号はそれぞれ同一もしくは相当部分を
示す0
FIG. 1 is a cross-sectional view showing an example of a conventional Brehner diode, and FIG. 2 is a cross-sectional view showing a Brehner diode according to an embodiment of the present invention. In the figure, (1) is the 1 type 81 substrate (the first conduction type semiconductor substrate), (21 is the p type 81 MI (the first conduction type semiconductor substrate)
+31 is the n-type 81 layer (the second semiconductor layer of the first great conduction type), (71 is the n-type 8i layer (the fifth semiconductor layer of the all conduction type). The same symbols in the middle indicate the same or equivalent parts 0

Claims (1)

【特許請求の範囲】[Claims] 111  高抵抗率を有し真性半導体として働く第1導
体層、上記半導体基板の上記181の主面部に上記第1
の半導体層との間に所定距離をおいてとのだものにおい
て、上記111および第2の半導体層間の上記所定距離
を上記真性半導体基板の上記第1および$5の半導体層
間の厚さより大きくしたこと1−特徴とするプレーナ形
ダイオード0
111 A first conductor layer having high resistivity and functioning as an intrinsic semiconductor, the first conductor layer having a high resistivity and acting as an intrinsic semiconductor, the first
in which the predetermined distance between the first and second semiconductor layers is greater than the thickness between the first and $5 semiconductor layers of the intrinsic semiconductor substrate. Thing 1 - Features of planar diode 0
JP17861681A 1981-11-07 1981-11-07 Planar type diode Pending JPS5879775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17861681A JPS5879775A (en) 1981-11-07 1981-11-07 Planar type diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17861681A JPS5879775A (en) 1981-11-07 1981-11-07 Planar type diode

Publications (1)

Publication Number Publication Date
JPS5879775A true JPS5879775A (en) 1983-05-13

Family

ID=16051554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17861681A Pending JPS5879775A (en) 1981-11-07 1981-11-07 Planar type diode

Country Status (1)

Country Link
JP (1) JPS5879775A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009094A (en) * 2013-02-25 2014-08-27 株式会社东芝 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148486A (en) * 1978-05-15 1979-11-20 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148486A (en) * 1978-05-15 1979-11-20 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009094A (en) * 2013-02-25 2014-08-27 株式会社东芝 Semiconductor device
JP2014165317A (en) * 2013-02-25 2014-09-08 Toshiba Corp Semiconductor device

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