JP2754947B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2754947B2
JP2754947B2 JP3124243A JP12424391A JP2754947B2 JP 2754947 B2 JP2754947 B2 JP 2754947B2 JP 3124243 A JP3124243 A JP 3124243A JP 12424391 A JP12424391 A JP 12424391A JP 2754947 B2 JP2754947 B2 JP 2754947B2
Authority
JP
Japan
Prior art keywords
region
type
well region
voltage
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3124243A
Other languages
Japanese (ja)
Other versions
JPH04350974A (en
Inventor
弘治 寺井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3124243A priority Critical patent/JP2754947B2/en
Publication of JPH04350974A publication Critical patent/JPH04350974A/en
Application granted granted Critical
Publication of JP2754947B2 publication Critical patent/JP2754947B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に中・高耐圧保護ダイオード素子の構造を考慮した半導
体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which the structure of a medium- and high-voltage protection diode element is considered.

【0002】[0002]

【従来の技術】通常のエンハンストランジスターのBV
DS耐圧は、10数Vであるが、例えば車のバッテリーに
接続するような場合、18V以上の耐圧のポートが必要
となる。
2. Description of the Related Art BV of a normal enhancement transistor
The DS withstand voltage is several tens of volts. For example, when connecting to a car battery, a port with a withstand voltage of 18 volts or more is required.

【0003】従来、この種の中・高耐圧ポートの保護ダ
イオードは、図3に示すように、Pウェル領域3の内部
にn+ 型領域6を形成し、n+ 型領域6から離して、素
子分離領域10の直下にチャネルストッパ領域11を設
け、アノード電極としてP+ 型領域7を形成する。この
中・高耐圧ダイオードは、Pウェル領域3とn+ 型領域
6によりPn接合を形成し、例えばPウェルをB+ 10
0Kev2.1E13の注入条件で1200℃2.5時
間で熱処理し、n+ 型領域をAs- 70Kev3.0E
15の注入条件で形成すると、このダイオードの逆方向
耐圧は20数Vとなり、所望の値が得られる。
Conventionally, the protection diode in, high-voltage port of this kind, as shown in FIG. 3, the n + -type region 6 is formed within the P-well region 3, apart from the n + -type region 6, A channel stopper region 11 is provided immediately below the element isolation region 10, and a P + type region 7 is formed as an anode electrode. The middle and high-voltage diodes, a Pn junction formed by the P-well region 3 and the n + -type region 6, for example, a P-well B + 10
Heat treatment was performed at 1200 ° C. for 2.5 hours under the implantation condition of 0 Kev2.1E13, and the n + -type region was changed to As 70 Kev3.0E.
When formed under 15 implantation conditions, the reverse breakdown voltage of this diode is about 20 V, and a desired value can be obtained.

【0004】次に保護素子としての動作を説明する。Next, the operation as a protection element will be described.

【0005】カソード電極が逆方向にバイアスされた場
合、耐圧はn+ 型領域6と素子分離領域10の接してい
る部分で決定されている為、n+ 型領域6の側面部から
電流は流れP+ 型領域7を通って、アノード電極にすい
とられる。従ってn+ 型領域6を大きくとり、側面長を
大きくすると、電流許容能力は向上し、それに伴って逆
方向バイアスされた場合のESD(静電破壊)耐量も上
がる。それに対し、カソード電極が順方向にバイアスさ
れた場合、コンタクト孔にセルフアラインに形成された
最も抵抗の低いn+ 型コンタクト領域5を電流は抜け
る。コンタクト孔の小さい領域に局部的に大電流が流れ
る為、Pn接合が容易に熱破壊してしまう。例えば、マ
シンモデルによるESD試験を行った場合、保護ダイオ
ードの大きさによらず100〜200V程度で破壊して
しまう。
[0005] If the cathode is biased in the reverse direction, since breakdown voltage that is determined in part in contact with the n + -type region 6 and the element isolation region 10, the current from the side surface of the n + -type region 6 flows It passes through the P + type region 7 and is used as an anode electrode. Therefore, if the n + -type region 6 is made large and the side surface length is made large, the current allowable capacity is improved, and accordingly, the ESD (electrostatic breakdown) resistance when reverse bias is applied is also increased. On the other hand, when the cathode electrode is biased in the forward direction, the current flows through the n + -type contact region 5 having the lowest resistance formed in the contact hole in a self-aligned manner. Since a large current locally flows in a small area of the contact hole, the Pn junction is easily thermally destroyed. For example, when an ESD test using a machine model is performed, the protection diode is broken at about 100 to 200 V regardless of the size of the protection diode.

【0006】[0006]

【発明が解決しようとする課題】この従来の耐圧が10
V代後半以上の中・高耐圧保護ダイオードは、カソード
電極がサージ電圧により順方向にバイアスされた場合、
コンタクト孔直下に電流が集中して流れてしまい、Pn
接合が容易に破壊し、保護能力が低いという問題点があ
った。
The conventional withstand voltage is 10
Medium / high withstand voltage protection diodes for the latter half of the V generation, when the cathode electrode is forward biased by the surge voltage,
Current concentrates and flows just below the contact hole, and Pn
There is a problem that the joint is easily broken and the protection ability is low.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
第1導電型の半導体基板の表面に第2導電型の第1領域
と、第1導電型の第2領域とを設け、前記第1領域と前
記第2領域との間で保護ダイオードを形成した半導体装
置において、前記半導体基板の表面に前記第1領域と重
複して第2導電型の第3領域を形成し、さらに、前記第
3領域の中に前記保護ダイオードの電極に接続される第
2導電型の第4領域を形成し、前記第3領域は、前記第
4領域及び第1領域より深い領域であることを特徴とす
る。
According to the present invention, there is provided a semiconductor device comprising:
A first region of a second conductivity type and a second region of a first conductivity type are provided on a surface of a semiconductor substrate of a first conductivity type, and a protection diode is formed between the first region and the second region. In the semiconductor device, a third region of a second conductivity type is formed on the surface of the semiconductor substrate so as to overlap the first region, and a second region connected to an electrode of the protection diode is formed in the third region. A fourth region of a conductivity type is formed, and the third region is a region deeper than the fourth region and the first region.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0009】図1は本発明の第一の実施例の断面図であ
る。P型半導体基板1にnウェル領域2を形成し、その
内部にダイオードのカソード電極とのコンタクトを採
り、nウェル領域2を包含するように大きくn+ 型領域
6を形成する。n+ 型領域6の側面部は素子分離領域1
0と接しPウェル領域3とオーバーラップするように形
成され、アノード電極としてPウェル領域3の内側にP
+ 型領域7を設ける。
FIG. 1 is a sectional view of a first embodiment of the present invention. An n-well region 2 is formed in a P-type semiconductor substrate 1, and a contact with a cathode electrode of a diode is formed inside the n-well region 2, and a large n + -type region 6 is formed so as to cover the n-well region 2. The side surface of the n + type region 6 is the element isolation region 1
0 and overlaps with the P-well region 3, and P is formed inside the P-well region 3 as an anode electrode.
A + type region 7 is provided.

【0010】カソード電極8が逆方向にバイアスされた
場合、濃度勾配の最も大きいn+ 型領域6の側面部で耐
圧は決定され、従来例で記述した拡散条件下で従来例と
同様の20数Vの耐圧を有する。
When the cathode electrode 8 is biased in the reverse direction, the breakdown voltage is determined on the side surface of the n + -type region 6 where the concentration gradient is the largest. It has a withstand voltage of V.

【0011】但しnウェル領域2とP型半導体基板1で
形成されるPn接合は最も濃度勾配が小さい部分で、カ
ソード電極が逆方向にバイアスされ最も空乏層が伸びき
った時に、Pウェル領域3に届かぬよう一定の距離nウ
ェル領域2とPウェル領域3は離しておかないと所望の
耐圧は得られない。この場合カソード電極8が逆方向に
バイアスされると従来例と同様にn+ 型領域6の側面部
からアノード電極9に電流は流れダイオードの側面長に
応じESD耐量は向上する。
However, the Pn junction formed by the n-well region 2 and the P-type semiconductor substrate 1 is a portion where the concentration gradient is the smallest, and when the cathode electrode is biased in the reverse direction and the depletion layer is fully extended, the P-well region 3 Unless the n-well region 2 and the P-well region 3 are separated from each other by a certain distance so as not to reach the desired voltage, a desired breakdown voltage cannot be obtained . If the current from the side surface of the conventional the cathode electrode 8 is reverse biased examples as well as n + -type region 6 to the anode electrode 9 This is the ESD immunity is improved according to aspects length of flow diode.

【0012】次にカソード電極8が順方向にバイアスさ
れた場合、n+ 型コンタクト注入領域5より深いnウェ
ル領域2が形成されている為に、最も抵抗の低いのはカ
ソード電極からnウェル領域2とn+ 型領域6の交線に
電流が抜けるパスで、従来例に示す場合と異なりコンタ
クト孔直下に集中的に電流が流れることはない。
Next, when the cathode electrode 8 is biased in the forward direction, since the n-well region 2 deeper than the n + -type contact injection region 5 is formed, the lowest resistance is from the cathode electrode to the n-well region. This is a path through which the current flows to the intersection of the n + -type region 2 and the n + -type region 6, and unlike the case shown in the conventional example, the current does not intensively flow directly below the contact hole.

【0013】図2は第一の実施例の平面図であるが、カ
ソード電極8が順方向にバイアスされた場合nウェル領
域2の側面に電流は抜け、nウェル領域2の大きさに比
例して電流許容能力は高まり、それに伴ってESD耐量
も向上する。従って、従来例と異なり集中して電流が流
れる部分が無い為に、例えばESD試験のマシンモデル
においてダイオードの側面長を500μm程度にしてお
けば、400V程度のESD耐量は得られ、従来例に対
しはるかにサージ電圧に対する保護能力は高まる。
FIG. 2 is a plan view of the first embodiment. When the cathode electrode 8 is biased in the forward direction, current flows to the side of the n-well region 2 and is proportional to the size of the n-well region 2. As a result, the current allowable capacity is increased, and the ESD tolerance is also improved accordingly. Therefore, unlike the conventional example, there is no portion through which current flows in a concentrated manner. For example, if the side length of the diode is set to about 500 μm in a machine model of an ESD test, an ESD resistance of about 400 V can be obtained. The protection ability against surge voltage is much higher.

【0014】図4は第2の実施例の断面図である。本実
施例も前実施例と同様にカソード部をn+ コンタクト注
入領域5より深いnウェル領域2で形成している為に、
アノード電極が順方向にバイアスされた場合において、
従来例のようにコンタクト直下に集中的に電流が流れる
ことはなくなり、nウェル領域2の大きさによりサージ
電圧に対する保護能力が決まってくる。又、アノード電
極が逆方向にバイアスされた場合、P型半導体基板1と
nウェル領域2のPn接合の濃度勾配が小さい為耐圧は
50〜60V程度と大きくなるものの、中・高耐圧端子
として動作上は全く問題はなく、順方向バイアスの場合
と同様nウェル領域2の側面長によりサージ電圧に対す
る保護能力は決定される。実施例2もダイオードの側面
長500μm程度でマシンモデルのESD試験に対し4
00V程度の保護能力を有する。
FIG. 4 is a sectional view of the second embodiment. In this embodiment, as in the previous embodiment, the cathode portion is formed by the n-well region 2 deeper than the n + contact injection region 5.
When the anode electrode is forward biased,
The current does not intensively flow immediately below the contact unlike the conventional example, and the protection capability against the surge voltage is determined by the size of the n-well region 2. When the anode electrode is biased in the reverse direction, the breakdown voltage becomes as large as about 50 to 60 V due to the small concentration gradient of the Pn junction between the P-type semiconductor substrate 1 and the n-well region 2. There is no problem at all, and the protection capability against surge voltage is determined by the side length of the n-well region 2 as in the case of the forward bias. In Example 2, the side length of the diode was about 500 μm, and the
It has a protection capacity of about 00V.

【0015】[0015]

【発明の効果】以上説明したように本発明は、中・高耐
圧保護ダイオードのカソード電極部にコンタクト注入層
より深いnウェル領域を形成することにより、サージ電
圧が印加された場合の保護能力高まるという効果を有
する。
The present invention described above, according to the present invention, by forming the deep n-well region than the contact injection layer to the cathode electrode of the medium- and high protection diode, the protection capability when a surge voltage is applied It has the effect of increasing.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図2】本発明の第1の実施例のカソード部平面図であ
る。
FIG. 2 is a plan view of a cathode section according to the first embodiment of the present invention.

【図3】従来例の断面図である。FIG. 3 is a sectional view of a conventional example.

【図4】本発明の第2の実施例の断面図である。FIG. 4 is a sectional view of a second embodiment of the present invention.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1導電型の半導体基板の表面に第2導
電型の第1領域と、第1導電型の第2領域とを設け、前
記第1領域と前記第2領域との間で保護ダイオードを形
成した半導体装置において、 前記半導体基板の表面に前記第1領域と重複して第2導
電型の第3領域を形成し、さらに、前記第3領域の中に
前記保護ダイオードの電極に接続される第2導電型の第
4領域を形成し、前記第3領域は、前記第4領域及び第
1領域より深い領域であることを特徴とする半導体装
置。
1. A first region of a second conductivity type and a second region of a first conductivity type are provided on a surface of a semiconductor substrate of a first conductivity type, and a first region of the second conductivity type is provided between the first region and the second region. In a semiconductor device having a protection diode formed thereon, a third region of a second conductivity type is formed on the surface of the semiconductor substrate so as to overlap with the first region, and further, an electrode of the protection diode is formed in the third region. A semiconductor device, wherein a fourth region of a second conductivity type to be connected is formed, and the third region is a region deeper than the fourth region and the first region.
JP3124243A 1991-05-29 1991-05-29 Semiconductor device Expired - Lifetime JP2754947B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3124243A JP2754947B2 (en) 1991-05-29 1991-05-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3124243A JP2754947B2 (en) 1991-05-29 1991-05-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04350974A JPH04350974A (en) 1992-12-04
JP2754947B2 true JP2754947B2 (en) 1998-05-20

Family

ID=14880511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3124243A Expired - Lifetime JP2754947B2 (en) 1991-05-29 1991-05-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2754947B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006319072A (en) * 2005-05-11 2006-11-24 Denso Corp Semiconductor device and its design method
JP5292067B2 (en) * 2008-11-20 2013-09-18 シャープ株式会社 Semiconductor device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168149U (en) * 1982-05-04 1983-11-09 三洋電機株式会社 transistor
JPH02134864A (en) * 1988-11-15 1990-05-23 Nec Corp Semiconductor integrated circuit with protective element

Also Published As

Publication number Publication date
JPH04350974A (en) 1992-12-04

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