JPH04364079A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration of characteristic due to the appearance of charges by forming an outer most surface layer having a first conductivity type and high impurity concentration to the region other than that having the second conductivity type in the low impurity concentration region. CONSTITUTION:A thin N layer is formed at the surface of a N<-> layer 2. A diode having the dielectric strength of 60V to 900V is fabricated using a silicon substrate having an N<-> epitaxial layer 2 of various impurity concentrations. In the diode having formed an N layer 12 having impurity concentration of 5X10<15>/cm<2> and diffusion depth of 1mum, operation life is extended. However, if impurity concentration of the N layer 12 is too high or diffusion depth is too deep, extension of depletion layer is remarkably interfered when an inverse bias is applied across an anode electrode 5 and a cathode electrode 6. Therefore, dielectric strength is lowered and it becomes difficult to suppress the surface sensitivity. In other words, the effective concentration range of the N layer 12 is 1X10<15> to 1X10<16>/cm<2> and diffusion depth range 18 0.2 to 2mum.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an electrode in contact with a diffusion region is formed on a semiconductor body and the surface thereof is then covered with a passivation film.

0002

[Prior art] An oxide film is formed on the surface of a silicon substrate,
Planar technology is well known in which impurities are diffused through the openings of the oxide film to form regions of a predetermined conductivity type in the silicon substrate, and electrodes are provided in contact with the regions within the silicon substrate through the openings of the oxide film. There is. In semiconductor devices based on such planar technology, an oxide film has a surface protection function.

[0003]Diode, transistor, MOSF
In order to increase the breakdown voltage of semiconductor devices such as ETs and IGBTs, it is common to lower the impurity concentration of the silicon substrate used. It is also known that it becomes more susceptible to the effects of surface charges. Therefore, in the sense of blocking external charges such as hydrogen ions, phosphorus glass (PSG)
) film or silicon nitride (SiN) film as a passivation film.

FIG. 3 shows the periphery of a silicon substrate of a conventional high voltage diode. A P-type anode is located at the center active region 21 of the silicon substrate, which consists of an N+ motherboard 1 and an N- epitaxial layer 2 thereon. A region 3 is formed, and the anode electrode 5 is in contact with the opening of the oxide film 4 on the surface. A cathode electrode 6 is provided opposite to the anode electrode 5 and in contact with the entire surface of the N+ layer. Voltage-resistant structure 2 against reverse voltage applied to anode electrode 5 and cathode electrode 6
2, there are a plurality of P-type guard rings 7 of the same depth formed at the same time as the anode region 3, in this case three,
Further, a P-type contact region 8 is formed at the end of the substrate, and a stopper electrode 9 having the same potential as the cathode electrode 6 is in contact with the side surface of the substrate via the contact region 8. Then, the anode electrode 5 excluding the exposed portion of the P region 8, the stopper electrode 9, the oxide film 4, and the connecting portion is made of, for example, Si.
It is covered with a passivation film 10 made of N film. FIG. 4 shows another conventional high-voltage diode, which differs from FIG. 3 in that a field plate 11 is provided on the surface of the voltage-resistant structure 22 in contact with the P-type guard ring 7 to have the same potential. It is that you are.

[0005]

[Problems to be Solved by the Invention] However, with the method of covering the passivation film to cut off charges such as foreign ions, if the film itself has minute defects such as pinholes and microcracks, the vapor of the semiconductor device may When conducting reliability evaluations such as pressurization tests, charges enter from minute defects and the state of the depletion layer changes, making it impossible to maintain the initial characteristics, resulting in increased leakage current, deterioration of withstand voltage, etc. Problems may occur.

An object of the present invention is to solve the above-mentioned problems and to provide a highly reliable semiconductor device in which characteristics do not deteriorate due to charge intrusion even if the passivation film has minute defects that are difficult to detect. be.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a second conductivity type region in a surface layer of a first conductivity type low impurity concentration region, and In a semiconductor device that is in contact with one of the main electrodes, an outermost surface layer of a first conductivity type and having a high impurity concentration is formed in a region of a low impurity concentration other than a region of a second conductivity type. The impurity concentration of the first conductivity type high impurity concentration outermost layer is 1 x 1015 to 1 x 1016/cm3, and the depth is 0.2.
~2 μm is effective. Further, a guard ring of the second conductivity type may be provided in the region of the outermost surface layer having a high impurity concentration of the first conductivity type, or a conductive field plate may be provided on the surface of the region.

[0008]

[Operation] By providing a high impurity concentration layer of the same conductivity type in the surface layer of a low impurity concentration region that is sensitive to surface charge, surface sensitivity can be suppressed, and even if there are defects in the passivation film, the semiconductor device The characteristics do not deteriorate.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention in a high voltage diode having a breakdown voltage structure 22 similar to that shown in FIG. 3, and parts common to those in FIG. The difference from the diode shown in FIG. 3 is that a thin N layer 12 is formed on the surface of the N- layer 2. A diode with such a structure is manufactured using a silicon substrate having an N- epitaxial layer 2 with various impurity concentrations to achieve a breakdown voltage class of 60V, 500V.
Manufactured for V class, 800 to 900 V class. The results of measuring the lifespan in the moisture resistance test are shown in FIG. In a conventional diode with the structure shown in Figure 3,
As shown by the solid line 31, the moisture resistance life is from 60V class to 5
As the impurity concentration of the N- epitaxial layer 2 is lowered to improve the withstand voltage from 00 V class to 800 to 900 V class, the lifetime becomes shorter. On the other hand, impurity concentration 5×1015/cm3, diffusion depth 1
In the diode having the structure shown in FIG. 1 in which the N layer 12 of .mu.m is formed, the decrease in lifetime is reduced as shown by the dotted line 32. However, if the impurity concentration in the N layer 12 is too high or its diffusion depth is too large, the anode electrode 5 and the cathode electrode 6
When a reverse bias is applied during this period, the elongation of the depletion layer is significantly inhibited, resulting in a drop in breakdown voltage, making it difficult to suppress surface sensitivity while maintaining breakdown voltage. That is, the concentration of the N layer is 1 x 1015 to 1 x 1016/cm3.
, a diffusion depth range of 0.2 to 2 μm was effective.

FIG. 2 shows another embodiment of the present invention in a high voltage diode having a voltage resistance structure 22 similar to that shown in FIG.
The same parts are given the same reference numerals. Also in this example, by forming the N layer 12, the same effect as shown in FIG. 5 could be obtained.

The present invention is not limited to diodes, but can be implemented in semiconductor devices such as planar high-voltage bipolar transistors, MOS field effect transistors, and insulated gate bipolar transistors, and can be implemented even when the low impurity concentration layer is N-type or P-type. can. It can also be applied to semiconductor devices without a stopper part of a voltage-resistant structure, a guard ring, or a field plate.

0012

According to the present invention, the surface sensitivity of a low impurity concentration region where a depletion layer extends when a reverse bias is applied is reduced by forming a shallow high impurity concentration layer of the same conductivity type in the outermost layer of the region. As a result, even if there is a defect in the passivation film, there is no deterioration in characteristics due to external charge, and a stable semiconductor device with a longer life in moisture resistance tests and the like can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the periphery of a high voltage diode according to an embodiment of the present invention.

FIG. 2 is a similar cross-sectional view of a high voltage diode according to another embodiment of the present invention.

[Figure 3] Similar cross-sectional view of a conventional high voltage diode

[Figure 4
】Similar cross-sectional view of another conventional high voltage diode

[Figure 5]
Relationship diagram between life and N-layer impurity concentration in the moisture resistance test of high voltage diodes shown in Figures 1 and 3

[Explanation of symbols]

1 N+ Silicon motherboard 2 N- epitaxial layer 3 P-type anode region 4 Oxide film 5 Anode electrode 6 Cathode electrode 7 Guard ring 10 Passivation film 11 Field plate 12 N layer

Claims (4)

[Claims] Claim 1: A region of a second conductivity type is provided in the surface layer of a region of a low impurity concentration of a first conductivity type, and one of the main electrodes is in contact with the region; A semiconductor device characterized in that a top surface layer of a first conductivity type and having a high impurity concentration is formed in a portion other than a region of a conductivity type. 2. The semiconductor device according to claim 1, wherein the high impurity concentration outermost layer of the first conductivity type has an impurity concentration of 1×10 15 to 1×10 16 /cm 3 and a depth of 0.2 to 2 μm. Claim 3: Claim 1, wherein a guard ring of the second conductivity type is provided in the region of the outermost surface layer having a high impurity concentration of the first conductivity type.
Alternatively, the semiconductor device according to 2. 4. The semiconductor device according to claim 1, wherein a conductive field plate is provided on the surface of the region of the first conductivity type highly impurity-concentrated outermost surface layer.