KR920000631B1 - Semiconductor device for high voltage and its manufacturing method - Google Patents

Semiconductor device for high voltage and its manufacturing method Download PDF

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KR920000631B1
KR920000631B1 KR1019880007206A KR880007206A KR920000631B1 KR 920000631 B1 KR920000631 B1 KR 920000631B1 KR 1019880007206 A KR1019880007206 A KR 1019880007206A KR 880007206 A KR880007206 A KR 880007206A KR 920000631 B1 KR920000631 B1 KR 920000631B1
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voltage
limiting ring
field limiting
semiconductor device
high voltage
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KR900000998A (en
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김종오
김진형
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현대전자산업 주식회사
정몽헌
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Priority to KR1019880007206A priority Critical patent/KR920000631B1/en
Priority to US07/364,624 priority patent/US5003372A/en
Priority to JP14857689A priority patent/JPH0715988B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor

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Abstract

The manufacturing method for high-voltage semiconductor element comprises (a) forming etched groove in the area for field limiting ring to be placed on the outer periphery of main joint part, (b) forming an insulation film on the etched groove, and (c) forming floating electrodes on the film to give a high blocking voltage. The insulation film is glass or corresponding insulating material. This invention can reduce the cost for designing break-down voltage, and make design conditions of seaiconductor substrate easier than before.

Description

고전압용 반도체 소자 및 그 제조방법High voltage semiconductor device and manufacturing method thereof

제1a도는 종래의 고전압용 반도체 소자의 단면도.1A is a cross-sectional view of a conventional high voltage semiconductor device.

제1b도는 종래의 고전압용 반도체 소자에서 필드 리미팅 링을 설치했을 때와 않했을 때의 전류, 전압특성 비교그래프도.FIG. 1B is a graph comparing current and voltage characteristics with and without a field limiting ring in a conventional high voltage semiconductor device. FIG.

제2도는 본 발명에 따른 고전압용 반도체 소자의 단면도.2 is a cross-sectional view of a semiconductor device for high voltage according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 전극 2 : 절연막1 electrode 2 insulating film

3 : P+확산영역 4 : N-에피텍셜 성장층3: P + diffusion region 4: N-epitaxial growth layer

5 : N+기판 6 : 전도물질5: N + substrate 6: conductive material

7 및 8 : 필드리미팅 링영역 9 및 10 : 부상전극7 and 8: field limiting ring region 9 and 10: floating electrode

본 발명은 고전압용 반도체 소자 및 그 제조방법에 관한 것으로, 특히 주접합 외곽에 필드 리미팅 링(FLR:Field Limiting Ring)을 설정하고자 하는 영역을 반도체 에칭(Etching)기술을 이용하여 홈을 파서 이 형성된 홈내, 외부상에 절연막을 형성한 후, 상기 에칭홈 부위에만 부상 전극을 형성시켜 높은 항복전압을 가지는 고전압용 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor device and a method of manufacturing the same. In particular, a groove is formed by digging a region in which the field limiting ring (FLR) is to be set around the main junction using a semiconductor etching technique. The present invention relates to a high voltage semiconductor device having a high breakdown voltage by forming floating electrodes only in the etching groove portions after the insulating film is formed in the grooves and on the outside.

종래의 고전압용 반도체 소자는 주접합 외곽에 필드 리미팅 링(FLR)영역을 형성하기 위하여 반도체 확산 방식에 의해 반도체 기판과 반대형(주접합과는 동일형)을 형성하여 제조하였으나, 300V이상의 고전압용에서는 필드 리미팅 링의 갯수가 증가하므로써 이에 대한 고전압용 반도체 소자의 제조설계에 난점이 수반되었다.Conventional high voltage semiconductor devices have been fabricated by forming the opposite type of semiconductor substrate (same type as the main junction) by the semiconductor diffusion method in order to form the field limiting ring (FLR) region around the main junction. As the number of field limiting rings increases, the manufacturing design of high voltage semiconductor devices has been difficult.

따라서, 본 발명은 필드 리미팅 링영역의 효과를 더욱 증대시키고, 제조를 간편히 하여, 종래의 고전압용 반도체 소자에서 블로킹(Blocking)할 수 있는 전압보다 더 높은 전압을 블로킹 할 수 있는 고전압용 반도체 소자 및 그 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention further enhances the effect of the field limiting ring region, facilitates manufacturing, and enables a high voltage semiconductor device capable of blocking a voltage higher than that which can be blocked in a conventional high voltage semiconductor device. Its purpose is to provide its manufacturing method.

본 발명에 의하면, 종래의 필드 리미팅 링 구조에서의 고전압 특성 효과가 더욱 증가되는데, 종래의 확산 방식으로 형성시키는 필드 리미팅 링영역을 본 기술에서는 실리콘 에칭기술(다른 어떠한 방법도 가능)을 이용하여 소정 깊이 만큼 에칭시켜서 홈을 형성한다음, 이 형성된 에칭 홈 내,외부에 절연막을 형성한 후 그 위에 전도물질로된 부상전극을 형성하여 결국 이러한 홈 구성이 종래의 필드리미팅 링의 역할을 함을 물론 더욱 향상된 고전압 특성을 갖는다.According to the present invention, the effect of the high voltage characteristic in the conventional field limiting ring structure is further increased. In the present technology, the field limiting ring region formed by the conventional diffusion method is determined by using silicon etching technique (any other method is possible). After etching to a depth to form a groove, an insulating film is formed inside and outside the formed etching groove, and then a floating electrode made of a conductive material is formed thereon, so that this groove configuration serves as a conventional field limiting ring. Further improved high voltage characteristics.

본 발명에 의하면, 종래의 주접합의 외곽 일부에 필드 리미팅 링영역을 설치하는 대신에, 반도체 에칭기술을 이용하여 에칭홈을 형성하는 공정과, 상기 에칭홈의 내,외부상에 절연막을 일정하게 형성하는 공정과, 상기 에칭홈에 도핑된 절연막 위에만 부상전극을 형성하는 공정으로 이루어진 것을 특징으로 한다.According to the present invention, instead of providing a field limiting ring region on the outer portion of the conventional main junction, an etching groove is formed using a semiconductor etching technique, and an insulating film is formed on the inside and the outside of the etching groove in a constant manner. And forming a floating electrode only on the insulating layer doped in the etching grooves.

또한, 본 발명에 의하면, 상기 형성된 홈의 내부에는 절연성이 좋은 유리로 채운다음 그위에 부상전극(Floating Electrode)을 형성시켰기 때문에, 상기 유리에 의한 전압 블로킹 능력이 더욱 부가되는 것이다.In addition, according to the present invention, since the floating electrode is formed on the inside of the formed groove with good insulating glass, the voltage blocking capability by the glass is further added.

따라서, 종래의 필드 리미팅 링에서는 여기에 인가된 전압과 반도체 기판내부에 형성된 전압의 양(Vflr+Vsub)만큼 만을 블로킹 할 수 있었으나, 본 발명에 의하면 상기의 전압양에 부가하여 상기 홈의 내부를 유리로 채운 구조에 의해 유리에서 블로킹하는 전압의 양이 가산됨으로써, 총전압의 양은 Vflr(에칭된 홈에 의한 전압)+Vsub(기판내부에 공핍된 전압)+Vglass(홈내부의 유리 절연막에 의해 형성된 전압)만큼 블로킹할 수 있게 되므로 종전보다 높은 전압을 블로킹하게 된다.Therefore, in the conventional field limiting ring, only the amount of voltage applied thereto and the amount of voltage (Vflr + Vsub) formed in the semiconductor substrate can be blocked. However, according to the present invention, the inside of the groove is added in addition to the voltage amount. The amount of blocking voltage in the glass is added by the structure filled with glass, so the total amount of voltage is Vflr (voltage due to the etched groove) + Vsub (voltage depleted inside the substrate) + Vglass (by the glass insulating film inside the groove). As the voltage can be blocked), a higher voltage than before can be blocked.

이하 첨부된 도면을 참조로하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a도는 필드 리미팅 링을 가지는 종래의 고전압용 반도체 소자의 단면도로서, 전극 애노드가 설치된 폴리실리콘등의 전도물질(6)상의 N+반도체 기핀(5)상에 N-에피텍셜 성장층(4)을 형성시키고, 그위에 P+반도체 영역(3)을 확산시켜 주접합을 형성한 다음, P+확산영역(3)위에 전도물질을 도핑하여 캐소드 전극을 인출시킨 주접합부가 형성되어 있다. 그런데, 여기에서는 P+확산영역(3)의 “A”부분에서 블렉 다운(Bre ak Down)되는 전압과 “B”부분에서 블렉 다운 되는 전압은 차이가 있기 때문에, 즉 “B”부분에서의 블렉 다운 전압이 “A”부분에서 블렉 다운되는 전압보다 훨씬 낮으므로 이를 완만히 보상하기 위하여 주접합 외곽의 일부에 P+확산영역(3)과 같은 확산영역(7 및 8)을 형성시키고(이 영역을 필드 리미팅 링 영역이라함) 그위에 절연체(2)를 형성하는 구조로 되어 있다. 여기서, P+확산영역의 블렉 다운 전압을 설명하기 위한 “A”및“B”부분을 포함하여 점선을 표시된 부분을 주접합부(Main Junction Part)라고 한다. 따라서, 종래의 필드 리미팅 링의 구조에서는 주접합부의 블렉 다운전압 특성효과를 보상하기 위하여 상기와 같이 필드 리미팅 링 영역을 다수로 구성하여 보완하였다.FIG. 1A is a cross-sectional view of a conventional high voltage semiconductor device having a field limiting ring, in which an N-epitaxial growth layer 4 is placed on an N + semiconductor pin 5 on a conductive material 6 such as polysilicon having an electrode anode. And a main junction formed by diffusing the P + semiconductor region 3 thereon to form a main junction, and then doping a conductive electrode on the P + diffusion region 3 to draw a cathode electrode. However, in this case, since the voltage that is blocked down in the “A” portion of the P + diffusion region 3 and the voltage that is down in the “B” portion are different, that is, the block down in the “B” portion. Since the voltage is much lower than the voltage that is blocked down in the “A” part, in order to compensate for this gently, diffuse areas 7 and 8, such as the P + diffusion area 3, are formed on the part of the main junction outside (the field limiting area). Ring region). The insulator 2 is formed thereon. Here, the portion indicated by the dotted line including the “A” and “B” portions for explaining the blockdown voltage of the P + diffusion region is called a main junction part. Therefore, in the structure of the conventional field limiting ring, a plurality of field limiting ring regions are configured and complemented as described above in order to compensate for the effect of the black down voltage characteristic of the main junction.

참고로, 종래의 고전압용 반도체 소자에서 필드 리미팅 링을 설치한 구조와 설치하지 않는 구조를 항복 전압과 함께 비교하기 위하여 주접합부만 가진 고전압용 반도체 소자와 여기에 필드 리미팅 링 구조를 취한 소자간의 V-I(전압-전류) 특성 비교그래프도인 제1b도를 참조하면 도면과 같이 항복전압의 크기에서 큰 차이를 보이고 있음을 알 수 있다.For reference, in order to compare the structure of the field limiting ring with the breakdown voltage in the conventional high voltage semiconductor device, the VI between the high voltage semiconductor device having only the main junction and the device having the field limiting ring structure therein Referring to FIG. 1B, which is a graph of comparison of (voltage-current) characteristics, it can be seen that there is a large difference in the magnitude of the breakdown voltage as shown in the drawing.

그러나, 이러한 종래 필드리미팅 링영역을 설치한 구조의 고전압용 반도체 소자에 불구하고 더욱 개선된 반도체 기술에서 요구하고 있는 소자로서는 블로킹 전압 특성이 양호하지 못하며, 그 제조방법에 있어서도 상기 필드 리미팅 링의 갯수가 많아짐에 따른, 설계 역시 매우 어려운 문제점이 있었다.However, despite the high voltage semiconductor device having such a structure of providing a field limiting ring region, the blocking voltage characteristic is not good as the device required by the improved semiconductor technology, and the number of the field limiting rings in the manufacturing method thereof is also good. As there were many, the design also had a very difficult problem.

제2도는 본 발명에 따른 고전압용 반도체 소자의 단면도로서, 주접합부 및 반도체소자 기본구성은 제1a도와 같은 구조이다. 그러나, 제1도의 주접합부 외곽에 형성된 필드 리미팅 링영역(7 및 8) 대신에 N-에피텍셜 성장층(4)상에 반도체 에칭(Etchin g)기술을 이용하여 요홈이 형성되도록 에칭시키고, 그위에 절연막(2)을 일정하게 도핑시킨다음, 상기 에칭된 홈의 절연막(2)위에만 폴리 실리콘등의 전도물질을 도핑하였다. 이 전도물질은 전기적으로 부상(Floating)되어 있기 때문에 이를 부상전극(9,10)이라 한다.2 is a cross-sectional view of the semiconductor device for high voltage according to the present invention, wherein the main junction portion and the basic structure of the semiconductor device have the same structure as in FIG. However, instead of the field limiting ring regions 7 and 8 formed outside the main junction of FIG. 1, etching is performed on the N-epitaxial growth layer 4 using a semiconductor etching technique to form a recess. After uniformly doping the insulating film 2, a conductive material such as polysilicon was doped only on the insulating film 2 of the etched groove. Since the conductive material is electrically floating, it is referred to as floating electrodes 9 and 10.

따라서 본 발명에 의해 이와 같이 구성된 영역을 종래의 필드 리미팅 링과 동일한 역할을 하게 됨은 물론, 전압 블로킹 능력을 크게 증가시키는 효과를 갖게 된다.Therefore, according to the present invention, the region configured as described above plays the same role as the conventional field limiting ring, and also has an effect of greatly increasing the voltage blocking capability.

상술한 바와 같이, 본 발명에 의하면 유리에 의해 부가된 고전압 블로킹 능력이 증가되는데, 필드 리미팅 링의 곡률반경에 따라 고전압 반도체 소자 양단에 인가된 BIAS에 의해 종래 소자의 고전압 블로킹의 양 Vblk은, 반도체기판 내부에 공핍된 (depleted)전압 Vsub에 필드 리미팅 링영역(7 및 8)에 형성된 전압 Vflr의 합으로 Vblk=Vsub+Vflr이 되지만, 본 발명의 고전압 블로킹 양 Vblk은 상기 Vblk의 양에 절연물(2)에서 형성된 전압이 부가되어,As described above, according to the present invention, the high voltage blocking capability added by the glass is increased, and the amount Vblk of the high voltage blocking of the conventional device is increased by BIAS applied across the high voltage semiconductor device according to the radius of curvature of the field limiting ring. The sum of the voltages Vflr formed in the field limiting ring regions 7 and 8 at the depleted voltage Vsub inside the substrate becomes Vblk = Vsub + Vflr, but the high voltage blocking amount Vblk of the present invention is equal to the amount of the insulating material (Vblk). The voltage formed in 2) is added,

Figure kpo00002
Figure kpo00002

로 되어, 결국, 종전보다 더 높은 전압을 블로킹할 수 있게 된다.As a result, it becomes possible to block higher voltage than before.

따라서, 본 발명의 구조에 의하면 항복전압(Break Down 전압)을 설계할시 설계비용을 대폭 줄일 수 있고, 필드 리미팅 링의 형성이 확산방식이 아니므로 반도체 기판의 설계조건이 용이하며, 특히 버티칼 더블-디퓨즈드 모스 에프이티(Vertical Double-Diffued Mos FET)의 설계에 본 발명의 방식을 이용할 경우 기판의 저항성분을 크게 감소시킬 수 있어 그에 따라 전류를 증가시킬 수 있으며 동일 칩 사이즈(Chip Size)에서 매우 높은 고전압 고전류의 반도체 소자를 형성시킬 수 있다.Therefore, according to the structure of the present invention, it is possible to greatly reduce the design cost when designing the breakdown voltage, and the design conditions of the semiconductor substrate are easy since the formation of the field limiting ring is not a diffusion method. Using the method of the present invention in the design of vertical double-diffued mos FETs can greatly reduce the resistivity of the substrate, thus increasing the current and at the same chip size. It is possible to form a semiconductor device of very high high voltage high current.

Claims (3)

필드 리미팅 링의 영역을 가진 고전압용 반도체 소자에 있어서, 주접합부의 외곽에 상기 필드 리미팅 링을 설치하고자 하는 영역에 에칭홈을 형성시키고, 이 형성된 홈상에 절연막을 형성한 후 그위에 부상전극을 형성시켜, 높은 블로킹전압을 갖도록한 것을 특징으로 하는 고전압용 반도체 소자.In a high voltage semiconductor device having an area of a field limiting ring, an etching groove is formed in an area of the main junction where the field limiting ring is to be installed, an insulating film is formed on the formed groove, and a floating electrode is formed thereon. To have a high blocking voltage. 제1항에 있어서, 상기 에칭홈에 도핑된 절연막은 유리 및 이에 상응하는 절연체인 것을 특징으로 하는 고전압용 반도체 소자.The semiconductor device of claim 1, wherein the insulating layer doped in the etching groove is glass and a corresponding insulator. 필드 리미팅 링의 영역을 가진 고전압용 반도체 소자 제조방법에 있어서, 상기 필드 리미팅 링의 영역을 설치하는 대신에, 주접합의 외곽의 N-에피텍셜 성장층상에 에칭홈을 형성하는 공정과, 상기 N-에피텍셜 성장층 및 에칭홈상에 절연막을 일정한 두께로 형성하는 공정과, 상기 에칭홈에 형성된 절연막 위에만 전도물질로 도핑시킨 부상전극을 형성하는 공정으로 이루어진 것을 특징으로 하는 고전압용 반도체 소자 제조방법.A method for manufacturing a high voltage semiconductor device having an area of a field limiting ring, comprising: forming an etching groove on an N-epitaxial growth layer outside the main junction, instead of providing an area of the field limiting ring; And forming a insulating film on the epitaxial growth layer and the etching groove to a certain thickness, and forming a floating electrode doped with a conductive material only on the insulating film formed on the etching groove.
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Publication number Priority date Publication date Assignee Title
KR101029328B1 (en) * 2008-09-22 2011-04-15 고려대학교 산학협력단 Field limiting ring and Method for configuring thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101029328B1 (en) * 2008-09-22 2011-04-15 고려대학교 산학협력단 Field limiting ring and Method for configuring thereof

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