JPS5750468A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5750468A
JPS5750468A JP12690280A JP12690280A JPS5750468A JP S5750468 A JPS5750468 A JP S5750468A JP 12690280 A JP12690280 A JP 12690280A JP 12690280 A JP12690280 A JP 12690280A JP S5750468 A JPS5750468 A JP S5750468A
Authority
JP
Japan
Prior art keywords
type
layer
region
informations
diffusing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12690280A
Other languages
Japanese (ja)
Other versions
JPH0318351B2 (en
Inventor
Osamu Hataishi
Kazuo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12690280A priority Critical patent/JPS5750468A/en
Publication of JPS5750468A publication Critical patent/JPS5750468A/en
Publication of JPH0318351B2 publication Critical patent/JPH0318351B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P34/42—

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To provide a semiconductor memory capable of writing, which has a short manufacturing time and a high degree of integration, by using radiation of an energy beam such as a laser beam or the like in order to write-in informations. CONSTITUTION:A linear buried electrode 12 becoming a line of matrix and an external region 13 at a crossing of matrix are formed on an N type silicon single crystalline substrate 11 by diffusing P type impurities. Then, an N type region 15 is formed in a P type layer 13 and an opening is formed in an SiO2 layer between the P type region 12 and an N-P type double layer region in order to form a polycrystalline silicon layer 16 doped into P type. Next, a metal electrode 18 connected to a P type region 15 of the N-P type double diffused layer is formed and a bonding pad 17 is formed. Writing-in of informations is carried out by applying a laser beam to the P type polycrystalline silicon layer 16, diffusing P type impurities in a single crystal, and connecting the P type buried electrode 12 and the P type region 15 through the P type diffused layer.
JP12690280A 1980-09-12 1980-09-12 Semiconductor memory Granted JPS5750468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12690280A JPS5750468A (en) 1980-09-12 1980-09-12 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12690280A JPS5750468A (en) 1980-09-12 1980-09-12 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS5750468A true JPS5750468A (en) 1982-03-24
JPH0318351B2 JPH0318351B2 (en) 1991-03-12

Family

ID=14946708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12690280A Granted JPS5750468A (en) 1980-09-12 1980-09-12 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5750468A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593254A (en) * 1979-01-05 1980-07-15 Univ Leland Stanford Junior Readdonly memory and method of programming same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5593254A (en) * 1979-01-05 1980-07-15 Univ Leland Stanford Junior Readdonly memory and method of programming same

Also Published As

Publication number Publication date
JPH0318351B2 (en) 1991-03-12

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