JPH0318351B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device. For more information,
Memory that constitutes a diode destruction type semiconductor memory device consisting of a diode matrix circuit
Concerning cell improvement. More specifically, the present invention relates to a diode-destructive semiconductor memory device in which the method for writing to each memory cell is simplified, the degree of integration is improved, and furthermore, the present invention does not require embedded electrodes.

It is well known that semiconductor memory devices are generally classified into MIS type, diode matrix array type, and amorphous semiconductor type. Among them, the diode matrix array type is further subdivided into a fixed matrix type, a fuse cut type, and a diode destruction type, but in all of the diode matrix array types, written information cannot be erased. However, in the case of a fixed mask type, the information is written in a fixed manner using the mask pattern used in the manufacturing process of the semiconductor memory device, whereas in the case of the fuse cut type and diode destruction type, the information is written in the same way as the semiconductor memory device. During the manufacturing process or after completion,
The difference is that this is accomplished by selectively passing a large current through a desired memory cell to blow out a fuse or destroy a junction diode.

See FIG. 1. FIGS. 1a and 1b show a perspective plan view and a cross-sectional view taken along line A-A of a portion of a memory cell region of a diode-destructive semiconductor memory device according to the prior art. In the figure, 1 is a P-type semiconductor substrate, and 2 is an N ⁺
It is a buried layer having a shape and extends in the vertical direction in FIG. 3 is a first PN junction, and 4 is a second PN junction, one of which is formed in each memory cell. 5 is an insulating layer, and 6 is the other electrode, which is electrically connected to the uppermost diffusion layer of the corresponding memory cell through an opening provided in the insulating layer 5, and in the left-right direction in FIG. It extends to form part of a column or row of a diode matrix. When writing information, a large current is passed from the electrode 6 toward the buried layer 2 at the matrix intersections that require rectifying conduction, destroying the second PN junction 4 and leaving only the first PN junction 3. A storage (memory) cell is configured. On the other hand, the first PN junction 3 and the second PN junction 4 are left at matrix intersections that do not require conduction to maintain insulation. The fuse cutting type differs in that a large current is passed through the matrix intersections where information needs to be written to blow out the fuses inserted at those intersections.

As mentioned above, the diode matrix array type semiconductor memory device requires a dedicated mask for a specific application in the case of a fixed mask type, which requires a considerable amount of time and cost to manufacture. The fuse cut type and diode broken type require a driver circuit with a large current capacity, and a considerable area of the semiconductor memory device is occupied by this driver circuit, resulting in a reduction in the degree of integration. has. Furthermore, regardless of the shape, N in the N ⁺ type buried layer 2
type impurities during subsequent epitaxial layer formation,
It has the disadvantage of diffusion into the epitaxial layer. In order to reduce this, the impurity concentration of the N ⁺ layer cannot be increased, resulting in an increase in series resistance in this part.

An object of the present invention is to solve these drawbacks in a diode matrix array type semiconductor memory device, and the two electrodes of a memory cell that are given rectifying conduction by writing information are both connected to a semiconductor device. The problem of high resistance of embedded electrodes, which was a major drawback in the conventional technology by disposing them flatly on the surface layer, has been solved, and information can be written by irradiating specific areas with energetic rays such as lasers, electron beams, or ion beams. The purpose of the present invention is to provide a memory cell having a structure that is made possible by the above method, and in the case of a fixed mask type, a dedicated mask is not required, thereby shortening the time and cost of manufacturing a semiconductor memory device. This not only makes it possible to improve the degree of integration by eliminating the need for a driver circuit in the case of a diode destruction type, but also improves the reliability of semiconductor memory devices by changing the buried layer method and reducing the electrode resistance as described above. It has unique effects such as improving

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the drawings, the structure of an embodiment according to the present invention will be explained following the manufacturing process to further clarify the structure and unique effects of the present invention. As an example, linear buried electrodes 12 made of a P-type diffusion layer are configured as rows or columns of a matrix on the surface layer of an N-type silicon (Si) single crystal layer whose surface is covered with an oxide film, just below the oxide film. N-P type double layer regions are scattered in parallel with this linear buried electrode 12, and an opening is provided in the oxide film on the N layer region of this double layer region. This opening and the other electrode 18 are ohmicly connected and constitute the columns or rows of the matrix, with the area between the double diffusion layer and the linear buried electrode being partially oxidized, for example. The film is removed to form an opening, and a P-type doped polycrystalline silicon (Si) layer, for example, is formed in the opening area, and each memory cell is formed with the above three elements. The storage (memory) cells existing at the matrix intersections that require conduction are exposed to the energy of laser, electron beam, ion beam, etc. in the P-type doped polycrystalline silicon (Si) layer region. The beam is selectively irradiated to convert the surface layer of the N-type semiconductor layer 11, including directly below this region, to P-type, and the two P-type regions that have been diffused in advance are short-circuited to select this memory cell. A diode destruction type semiconductor memory device including a plurality of memory cells having a structure that provides rectifying conduction is cited.

Refer to Figure 2. The first step involves using an oxide film formed on an N-type silicon (Si) single-crystal substrate or layer as a mask to form regions in rows or columns of a matrix, and in parallel with the regions in rows or columns of a matrix. Alternatively, it is a process of selectively forming P-type diffusion regions in regions intersecting rows. Such an N-type silicon (Si) single crystal layer may be an N-type epitaxial layer formed on a P-type silicon (Si) single crystal layer. A plan view and a cross-sectional view of a portion of the wafer after this process is completed are shown in Figure 2a,
Shown in b. In the figure, 11 is an N-type silicon (Si) single-crystal layer, and 12 is a P-type diffusion region forming a linear buried electrode serving as a row or column of a matrix. Reference numeral 13 denotes a P-type layer on the outside of the NP-type double layer region which is scattered in parallel with the linear embedded electrodes 12 and is the intersection point of the matrix. 14 is a silicon dioxide (SiO ₂ ) film. The linear buried electrode 12 extends in a desired direction and constitutes one electrode of all memory cells belonging to a particular row or column.

Refer to FIG. 3. The second step is a step of selectively forming an N-type region 15 in the P-type layer 13 formed in the previous step using a silicon dioxide (SiO ₂ ) film or the like as a mask. A plan view and a cross-sectional view of a portion of the wafer after this process is completed are shown in FIGS. 3a and 3b.
In the figure, 15 is an N-type region formed in this step.

Refer to FIG. 4. In the third step, a part of the silicon dioxide (SiO ₂ ) film 14 in the region between the P-type region 12 and the N-P type double layer region 15-13 is removed to form an opening. , in which a P-type doped polycrystalline silicon (Si) layer 16 is deposited in the opening. A normal etching method can be used to remove a part of the silicon dioxide (SiO ₂ ) film 14, and
As a method for forming the P-type polycrystalline silicon (Si) layer 16, an ordinary chemical vapor phase growth method can be applied.
A plan view of a portion of the wafer after this process is completed and D
-D sectional views are shown in FIGS. 4a and 4b. In the figure, numeral 16 is a P-type polycrystalline silicon (Si) layer, which is in direct contact with the N-type silicon (Si) single crystal layer 11.

Refer to Figure 5. The fourth step is the N-P type double layer region 15-1.
A part of the insulating film 14 made of silicon dioxide (SiO ₂ ) on the N-type region 15 inside 3 and a part of the insulating film 14 made of silicon dioxide (SiO ₂ ) on the linear buried electrode 12 (bonding pads) (formation area)
A process of forming openings by removing the electrodes 18 and arranging the bonding pads 17 of the linear embedded electrodes 12 forming the rows or columns of the matrix in the former and forming the electrodes 18 forming the columns or rows of the matrix in the latter. It is.
A conventional etching method can be used to remove a portion of the silicon dioxide (SiO ₂ ) film 14, and a conventional etching method can be used to form the electrodes and bonding pads, such as metal vapor deposition, sputtering, and subsequent selective etching. An ohmic electrode formation method is applicable. A plan view and a sectional view of a portion of the wafer after this process is completed are shown in FIGS. 5a and 5b. In the figure, 17 is a bonding pad of the linear buried electrode 12, 18 is an electrode constituting the column or row of the matrix, and the N-type layer inside the N-P type double diffusion layer 15-13. It is connected to 15 and Ohmic.

In the above description, only the process of forming a memory cell, which is the gist of the present invention, has been described, but the read driver circuit, which is naturally necessary for a diode matrix array type semiconductor memory device,
Needless to say, multiplexer circuits, output circuits, etc. are also formed in parallel.

Next, the information writing operation will be explained. As is clear from FIGS. 5a and 5b, bonding pads 17 and electrodes 18 are connected at each intersection of the matrix.
Since there is a P-N-P-N junction between the two, there is no conduction in either direction. Therefore, for memory cells existing at matrix intersections that require rectifying conduction, a laser beam is selectively applied to the P-type polycrystalline silicon (Si) layer 16 region.
P-type impurities are diffused from this P-type polycrystalline silicon (Si) layer 16 into the single-crystalline silicon (Si) layer 11 by irradiating energy rays such as electron beams and ion beams, and this polycrystalline silicon (Si) In the lower region of layer 16, P-type linear buried electrode 12 and N-P
P-shaped region 13 outside the shaped double layer region 15-13
and are connected by a P-type diffusion layer. As a result, the linear buried electrode 12 (bonding pad 17) and the N-P
N-type region 15 inside the shaped double layer region 15-13
There is only one P-N between region 13 and region 15 between
A junction remains, forming a memory cell having rectifying conduction from the electrode 12 to the electrode 18, in which information is written.

As explained above, since information is written by selective irradiation with energy rays, in the case of a fixed mask type, there is no need to manufacture a mask for writing information, and it is easier to manufacture semiconductor memory devices. It becomes possible to shorten time and reduce costs, and P
- In the case of a diode destruction type including ROM, there is no need for a driver circuit for writing information, and the integrated circuit can be improved. Furthermore, as is clear from a comparison between Figures 1a and b and Figures 5a and b, the manufacturing process is rather simplified;
In particular, the structure of the present invention employs a linear buried electrode 12 having a structure completely different from that of the buried electrode 2 shown in FIGS. 1a and 1b. The surface resistance is improved by one order of magnitude to several ohms/hole, rather than several tens of ohms/hole as in the case of electrode 2. Although there is an undeniable tendency for the area occupied by the memory cell itself to become somewhat larger, the overall degree of integration is improved because the driver circuit is eliminated. Furthermore, since the P-type regions 12 and 13 can be formed in a self-aligned manner with a silicon dioxide (SiO ₂ ) layer serving as an isolation layer, this contributes to the integration of the device as a whole.

As explained above, according to the present invention, information can be written using energy beams in a diode matrix array type semiconductor memory device, regardless of whether it is a fixed mask type or a diode destruction type including a P-ROM. Since this is possible through selective irradiation, the information writing method is simplified, a mask is not required for the fixed mask type, and the degree of integration is improved for the diode destruction type. Moreover, it is possible to influence a highly reliable semiconductor memory device in which the resistance of the buried electrode is low.

In the above explanation, N-type silicon (Si)
Although a row using a single crystal layer is shown, this is only an example, and it goes without saying that it is not limited to N-type, and can also be manufactured using semiconductors other than silicon (Si).

[Brief explanation of the drawing]

FIGS. 1A and 1B are a perspective plan view and a cross-sectional view taken along the line A-A of a portion of a memory cell region of a diode-destructive semiconductor memory device according to the prior art. Figure 2 a, b, Figure 3 a, b, Figure 4 a, b, Figure 5
Figures a and b show the first step and the second step, respectively, of the method for manufacturing a diode-destructive semiconductor memory device according to the present invention.
FIG. 3 is a perspective plan view and a cross-sectional view of the wafer in the memory cell region after completing the process, the third process, and the fourth process. DESCRIPTION OF SYMBOLS 11... Semiconductor single crystal layer, 12... Linear buried electrode, 13... Outer layer of double layer region, 14... Insulating layer, 15... Inner layer of double layer region, 16... Doped multilayer Crystalline semiconductor layer, 17... Bonding pad for linear buried electrode, 18... Electrode.

Claims (1)

[Claims] 1. In a diode destruction type semiconductor memory device comprising a diode matrix circuit formed on a semiconductor single crystal substrate or layer of one conductivity type, a second opposite conductivity type region 13 disposed on the surface of the semiconductor substrate or layer 11 at a distance from the first opposite conductivity type region, and the second opposite conductivity type region 12; one conductivity type region 15 formed in the region 13; and an opposite conductivity type impurity source disposed on the semiconductor substrate 11 between the first opposite conductivity type region 12 and the second opposite conductivity type region 13. 16, wherein information is written by irradiating the opposite conductivity type impurity source 16 with an energy beam.