NL8301234A - PROGRAMMABLE READING MEMORY AND METHOD FOR MAKING THEREOF - Google Patents

Description

* ΡΗΑ..1067 1 N.V. Philips' Gloeilampenfabrieken in Eindhoven. Programmable reading memory and method for manufacturing it.

The invention relates to a programmable read memory (PRQM) in a semiconductor body having a recessed electrically insulating region on a first surface and a single crystalline semiconductor region adjoining it, with a number of laterally separated memory cells along the surface, each cell having a substantially horizontal first pn junction, located in the semiconductor region, and having a corresponding second pn junction, which together form a pair of 10 pn junction diodes connected against each other. Each memory cell contains a pair of opposing diodes, one of which can be selectively destroyed to program the memory. In addition, the invention relates to a method for manufacturing such a memory.

15 Programmable reading memories (PROMs) are becoming increasingly important in electronic memory applications. Of particular interest is the type of programmable read memory having an array of rows and columns of memory cells each consisting of a pair of pn junction diodes connected against each other. A first of the diodes in each cell serves as a matrix element for electrically insulating the cell, while the second diode can be selectively destroyed to program a logic "O" or a logic tt1 "in the cell. The programmable diode is destroyed in practice by forcing a sufficiently high reverse current through its pn junction, so that this junction is permanently short-circuited.

An electrically insulating material, such as silicon dioxide, is used to laterally separate the memory cells from each other in known programmable read memories of the above-mentioned type. British Patent No. 2OO5079 discloses such a programmable read memory, wherein each matrix diode is a vertical diode, 8301234 1 (PHA.1Ο67 2 «, * whose pn junction is horizontal in a single crystalline silicon region of a semiconductor body and laterally completely through a silicon dioxide sunken region is limited Each programmable diode is a horizontal diode, the pn junction of which is located in a polycrystalline silicon region adjacent to the top surface of the single crystal line region. transition of each programmable diode generally extends perpendicular to the lower-plane νειη the body This programmable reading memory is manufactured by forming an n-type epitaxial layer on the top surface of a p-type substrate and then to form a p-type epitaxial layer on the n-type epitaxial layer A deep n-type region touches the lower face of the deep oxide region, which i s formed around parts of the epitaxial layers to form the matrix diode. At the location of each cell, there is an opening in an insulating layer, covering the p-type epitaxial layer. The pn junctions for the programmable diodes 20 are formed in a polycrystalline silicon layer deposited on the insulating layer and on the portions of the p-type epitaxial layer exposed through the apertures.

Although relatively small currents of about 20 mA are required to program this programmable read memory, its horizontal diodes increase the space space a cell occupies. Moreover, the properties of pn junctions in polycrystalline silicon are less easily controllable during manufacture than those in single crystalline silicon.

Another similar programmable read memory is described in European Patent No. 0018173 · In each memory cell of this programmable reading memory, the pn junctions of the two diodes are located in a single crystalline silicon region. An insulating region containing silicon dioxide directly adjacent to a single crystalline region separates the cells laterally. Each pn junction is nearly horizontal in the center 8301234 PHA..1067 3 4 * ........ v * of its cell and extends upward to the top face of the single crystalline region at a point that spaced from the side walls of the insulating area.

The pn junction of each matrix diode surrounds the pn junction of the corresponding programmable diode. This programmable reading memory is manufactured by selectively forming buried n-type regions along the top surface of a p-type silicon substrate, after which an n-type epitaxial layer is formed on the top surface of the substrate. The lateral isolation regions are then formed, and the pairs of pn junctions are obtained by forming p-type regions in the epitaxial layer above the buried regions and forming n-type regions in the p-type regions.

Although shallow regions can be used in this programmable read memory to define the diodes, by enclosing the diode, in each cell, the space occupied by the cell becomes relatively red due to tolerances in the photolithographic alignment. The memory takes up about 9 (yum). As a result, the programming current increases. In addition, parasitic transistor operation during programming of a cell in one buried region can cause the pn junction between the aub-25 and another buried region to be biased in the forward direction, so that the programmable diode in the cell along the same column in the other buried area is damaged.

A programmable read memory according to the invention is characterized in that every second pn junction is substantially horizontal and is above the corresponding first pn junction, such that the intermediate region common to each pair of diodes between the pn junctions is completely is limited by the insulating region. Preferably, every second pn junction is in the semiconductor region,

The expression "substantially horizontal", when applied to the pn junctions of the cells, means that 8301234 PHA each. 1067 4 _ * <• * thereof lies largely in a plane, which is parallel to a substantially flat lower surface of the semiconductor body. Each transition is "substantially horizontal" even if it is slightly up (down) where it abuts the iso-learning region. Thus, the two diodes in each programmable memory cell are vertical diodes. The bottom diode, defined by the first pn junction, is normally the trigger element, while the top diode, defined by the second pn junction, is normally the programmable element. By ensuring that the pn junctions in each cell are completely adjacent to the insulating region, the present programmable read memory takes up very little space. In practice, the memory element in each cell takes up about 2.25 µm, which is much less than in comparable known devices.

The maximum of the dopant concentration in each intermediate region is preferably between the two pn junctions and optimally near the mid-point between the two pn junctions. This doping profile, which is obtained by ion implantation, facilitates the production of a programmable reading memory and improves programming.

The bottom cell areas immediately below the first 25 pn junctions are of a first conductivity type, while the intermediate cell regions are of an opposite second conductivity type. The cells are normally formed above a substrate region of the second conductivity type. Therefore, a problem arises in that the substrate region may act as the collector for a parasitic transistor, in which the lower region of each cell serves as the base and the adjacent intermediate cell region is the emitter. When the second pn junction of this cell is destroyed, its first 35 pn junction is biased in the forward direction, thereby conducting the associated parasitic transistor. The current injected into the substrate region by the parasitic transistor would cause the voltage to be 8301234 PHA there. 1067 5

* '** I

increase sufficiently to cause the pn junctions between the substrate and the bottom cell regions of other cells to be biased along the same column in the forward direction. As a result, the second pn-transitions of these other cells can then again be adversely affected.

To overcome this problem and also to establish electrical interconnections to the lower cell regions, an assembled 1B digging layer is advantageously used. This buried layer contains a number of highly doped buried areas of the first conductivity type directly below the lower cell areas. Each buried area is adjacent to the insulating area along the entire bottom perimeter of each of one or nut associated lower cell areas. By ensuring that the buried areas come into contact with the insulating area, the gain of each parasitic transistor is significantly reduced, in a practical example by a factor of 100. As a result, the one in the substrate area during the programming of one cell is obtained. voltage is significantly reduced so that programmable diodes in other cells along the same column are protected.

The semiconductor body preferably contains a highly doped buried network of the second conductivity type, which laterally surrounds each buried region. The buried network forms a low resistance path for the discharge of charge carriers injected into the substrate region by the parasitic transistors during programming to prevent further enhancement of the substrate potential.

The buried network is laterally separated from the buried area by a layer of doped area, which contains the substrate area and extends up to the insulating area. The low-doped region serves to increase the breakdown voltage of the pn junctions of the substrate to an acceptable value.

A great advantage of the present memory is that it is very insensitive to many defects caused by materials and processes. Only the actual memory element area of each cell is highly susceptible to such defects and this area is very small. Terminals extending through the insulating region g to the composite buried layer are highly insensitive to many of these defects, while many of the pn junctions are protected in whole or in part by the insulating region. Therefore, this programmable read memory is very suitable for the manufacture of very large memory arrays.

In the manufacture of the programmable reading memory, the insulating region is first formed such that it completely abuts the entire circumference of each of a large single crystalline portions of a doped region of the first conductivity spaced apart from one another. the area of the doped area are located. Via the surface, the single crystalline parts are a dopant of the second conductivity type doped to define the first pn junctions. The second pn junctions can be similarly applied via the surface in each monocrystalline part with a dopant of the first conductivity type.

Preferably, the insulating region is used as a mask to control the lateral spread of this 2g dopant and in each single crystal portion. Preferably, a second conductivity type dopant is applied by ion implantation and the programmable read memory is then fired at a temperature sufficiently low to restore any lattice damage due to the dopant introduction without significant redistribution of the dopants or other impurities previously made in the programmable read memory takes place.

The composite buried layer and the insulating region are normally formed at an earlier stage in the manufacture of the programmable read memory.

One impurity causing the first conductivity type 8301234 * PHA. IO67 7

* J

It is selectively applied * in a single crystal semiconductor substrate of the second conductivity type at a plurality of first locations spaced along a surface of the substrate to define the buried regions. Preferably, the buried network is also defined by selectively an impurity causing the second conductivity type. into the substrate in a second place, each. of the first places and is located at a distance therefrom. An epitaxial semiconductor layer is then grown on the surface of the substrate.

A network-shaped part of the epitaxial layer is removed along its top surface to form a depression. The substrate and the remainder of the epitaxial layer are then selectively exposed at high temperature to an evolving atmosphere to oxidize a portion of the epitaxial layer along the depression, thereby forming the insulating region and effecting a some of the impurities deposited in the 2Q substrate diffuse up into the epitaxial layer to form the composite buried layer.

The invention will now be explained in more detail with reference to an exemplary embodiment and the drawing, in which fig. 1 schematically shows a top view of an embodiment of a programmable reading memory according to the invention, FIGS. 2a and 2b show cross sections of the embodiment in FIG. 1 according to planes 2a-2a resp.

3Q 2b-2b in Fig. 1, Figures 3a-3n show cross-sectional side views during various stages of a process for manufacturing the embodiment in Figures 1, 2a and 2b.

The cross section of each of Figures 3a-3n corresponds to the cross section of Figs. 2a.

and FIG. 4 shows a graph of the doping concentration of a specific programmable reading memory cell according to the invention.

8301234 IPhA IO67 8

The same reference numerals are used in the drawings and in the description of the preferred embodiment to indicate the same (the same) or a similar element (similar elements). In general, the dimensions in the drawings are not drawn in scale for clarification of the illustration.

Fig. 1 is a cross-sectional view of a preferred embodiment of a programmable read memory containing a group of identical programmable read memory cells, each consisting of a pair of oxide-insulated vertical diodes.

Figures 2a and 2b show perpendicular cross-sectional side views of the embodiment in Figs. 1 illustrating the structure of the programmable read memory in a semiconductor body with a planar bottom face 10. As shown in FIGS. 2a and 2b, the view of FIG. 1 according to plane 1-1 parallel to the lower plane 10. The plane shown in FIG. 1 elements indicated by dotted lines are below plane 1-1.

20 The terms "bottom", "bottom", "top", "top", "bottom", "top", "vertical", "horizontal" and "lateral" are clearly defined with respect to the orientation of the semiconductor body with the surface 10 parallel to the earth.

The EROM packages are arranged in a matrix of rows and columns. The rows are spaced about 20 µm apart.

Six BROM cells 12 ^, 12 ^, 12j ,, 12 ^ f, 12 ^ 'and 12 ^' are shown in FIG. 1 is displayed. Cells 12 ^, 12 ^ and 12 ^ 30 lie in one row, while cells 12 ^ ', 12 ^ * and 12-p' lie directly opposite in an adjacent row. Thus, each index "B", "D" or "F" indicates a special column; the non-accentuated symbols represent the ones shown in FIG. 2a, while the 35 accented symbols indicate the adjacent row. Some of the regions located between the columns are indicated by reference numerals with the corresponding alternating indices "A", "C", "E" and "G". Referring to a 8301234 PHA IO67 9 random cell of cells 1 ZB '12D * 12F * 12B,> 12d' and 12 - »*, their components or separate column elements, separated by indices" B ", "Dn or ttF", or to any area of the areas, where -5 of the reference characters contain the indices "A", "C", "E" and rtG ", the indices are" A "to" G · ” and the accents in this description are generally omitted, although they are shown in the drawings as part of the full reference numerals In addition, the components of the cells 12 in the drawings are not, or only partially, referenced to avoid a vast amount of indications For example, only the components of the cell 12jj in Figures 2a and 2b are fully indicated.

The cells 12 are formed in a doped monocrystalline region of the body along an upper surface 1k of the monocrystalline region and are separated laterally by adjacent parts of a galvanizing network-insulating region 16 of silicon dioxide which is selectively is disposed in the body along the surface 14. The single crystalline region in Figures 2a and 2b is that portion located between the surfaces 10 and 14, excluding the insulating region 16. The center-to-center distance of portions of the insulating oxide region 16 on opposite sides of each cell 12 along a row is approximately 11 µm. The oxide region 16 has bird basin 18, which penetrate into the one-crayon region, narrowing each cell 12 along the surface 14 to a cross section of about 2.25 µm. From the surface 14, the bottom face of the oxide region 16 is at a depth of about 1.1 µm.

Each cell 12 consists of a lower matrix diode and an upper programmable diode. The matrix diode is a vertical pn junction element formed by a lower n region 20 and an intermediate p region 22, the common interface of which defines a first pn junction 26 with a lateral surface of byum and a breakdown voltage of approximately 16 V. The 8301234

I I

PHA. IO67, 10 programmable diode is a vertical pn junction element consisting of the ρ region 22 and an upper n region 28, the common interface of which is a second pn junction 30 with a lateral area of about 2.5 µm and a breakdown voltage of about 6 Y. The difference in surface area of the transitions is due to the deeper penetration of the bird's beak 18 into the cell 12 along the transition 30. The larger surface area of the transition 26 serves to prevent, that this transition is adversely affected when the programmable diode is programmed.

The p region 22 is entirely delimited by the insulating region 16, as are the pn junctions 26 and 30. Each pn junction 26 or 30 is horizontal over most of its surface, but in practice it extends up near the point where it is adjacent to the edges of the oxide region 16. Since the center of each transition 26 or 30 is parallel to the bottom surface 10 and the upwardly extending portion of the transition 26 or 30 is very small, the transitions 26 and 30 become properly characterized as “virtually horizontal”.

As will be described in more detail below, the maximum concentration for the p-type dopant in the p-type region 22 occurs between the transitions 26 and 30 (instead of the transition 30). Desirably, the point where the maximum p-type concentration is present in the intermediate region 22 is a vertical distance from the point midway between the transitions 26 and 30, which is not greater than 20% of the distance transitions 26 and 30. Optimally, the maximum p-type concentration occurs approximately halfway between transitions 26 and 30. In case the regions 20, 22 and 28 could be considered as an npn transistor with a permanently floating (not connected) base, the use of such dopant distribution makes a potential transistor operation ineffective because the intermediate region 22 is wider than a conventional transistor base, so that the current 8301234 PHA. 1067 11 gain is very small (about 2). In addition, this doping distribution facilitates the production of a programmable read memory in large matrices, because a high p-type concentration exists along the walls 5 of the oxide region 16, thereby reducing the chance of shorting by an inversion path or other defective mechanism.

The cells 12 are formed as the top part of a structure in which electrical connections are to be made between the bottom n regions 20 and the conductors for the rows of the programmable read memory. The bottom part of the structure basically consists of a layer of doped p-type semiconductor substrate. In the absence of a buried layer with strongly doped n-type and p-type regions, each p-region 22 serves as an emitter for a vertical parasitic pnp transistor, the base of which is the adjacent n-region 20 and the collector of which remains low-doped p-type is part of the substrate.

During the part programming, the potential of all 3i regions 28 along a particular column is increased by increasing the potential of the column conductor connected to these n + regions 28. When a special cell 12, such as cell 12 ^, is programmed, avalanche breakdown of the pn junction 30 ^ occurs, whereby; current is caused to flow in the p region 22 ^ and in the pn junction 26 ^ which is biased in the forward direction. Therefore, the pnp parasitic transistor associated with this cell 12 ^ can become conductive. The base-collector junction for this vertical parasitic transistor is the base-emitter junction for a lateral npn parasitic transistor, the base-collector junction of which is formed by the remaining low-doped p-type substrate part and the n-region 20 from any other cell 12, such as cell 12 *, along the same column.

When the pnp parasitic transistor becomes saturated, its base-collector junction is biased in the forward direction, so that the substrate 8301234 PHA. 1067 12 voltage is increased such that the lateral npn transistor becomes conductive. Therefore, the voltage of the n region 20D 'is lowered to almost that of the n region 20β and the pn junction 30 ^ * can be adversely affected, because the n + region 28 ^' is at the same potential as the n + area 28 ^. Briefly, the operation of the pnp parasitic transistor associated with each cell 12 being programmed can damage the programmable diodes of other cells 12 along the same column. To overcome this problem, a composite buried layer is used at the cells 12 to establish electrical interconnections with the word lines and to provide further electrical isolation between the rows.

One portion of this composite buried layer consists of a pair of buried n + regions 32 which lie directly below the lower n region 20 and smoke on the lower surface of the oxide region 16. Preferably, each buried area 32 forms a continuous whole with four of the lower areas 20. For the sake of clarity of the drawings, however, each area 32 is shown in Figures 1, 2a and 2b as if it were a continuous whole with only two of the lower regions 20. For example, the buried region 32q is shown, as if it forms a continuous whole with the lower regions 20β and 20-β. Therefore, each region 32 is adjacent to the insulating region 16 along the entire lower circumference of each lower region 20, which is contiguous with the respective region 32.

The average net dopant concentration in the * 18 3 buried areas 32 is approximately 1.6. 10 atoms / cm. The lower regions 20 have a relatively uniform net dopant concentration of about 8. 10 J atoms / 3 cm, to which value the concentrations of regions 32-35 fall back along said region 16, where they. converge with the areas 20 (about 1.0 µm below the surface 14). The buried areas 32 extend to about kyrum from the surface 14 in the body.

8301234 PHA. 1067 13

Each of the areas 32 extends. into a doped p-type substrate region 34, the lower boundary of which is formed by the surface 10, thereby forming an insulating p-junction 36, which is normally biased g in the reverse direction. The p region 3k has a relatively uniform net dopant concentration of about 1. 10 ^ atoms / cm ^. This is also the n-type doping concentration, of the buried areas 32 along the insulating transitions 36.

jq The insulating transitions 36 are the basic collector transitions for the pnp parasitic transistors, which may become conductive during programming. Since each buried region 32 is completely adjacent to the oxide region 16 surrounding each associated cell 12, the n + -jg regions 32 are part of the bases of the pnp parasitic transistors. Therefore, their current gain is lowered from about 10, in the absence of regions 32, to about 0.1. When one of the cells 12 is programmed, the diminished gain decreases the 2q voltage, which can be built up in the substrate region 3 ^. This prevents the programmable diodes from other cells 12 in the same column from being damaged.

Each buried area 32 is connected to the surface 14 through an associated n + composite area 38, which consists of a lower n + region 40 and an upper n + region 42. The combination of n + regions 32 and 38 provides the necessary interconnections between the lower cell areas 20 and the row guides. The high doping in each buried region 32 serves to decrease the series-30 resistance between its terminal region 38 and its lower cell regions 20. The terminal regions 38 also form paths of low resistance to the surface 14, to avoid the parasitic voltage drops which occur during the cell programming to occur.

The other part of the composite buried layer is a buried p + network 44, which laterally surrounds each of the buried n + regions 32. Buried network 44 smokes at the bottom of the insulating area 16 and extends 8301234 PHA 1067. partly upwards along its side walls.

The average net dopant concentration in the p + network 44 is about 7 · 10 atoms / cm. Buried network 44 has a net dopant concentration of about 5 L. 10 'atoms / cm 2 at the point where it touches the underside of the oxide region 16, while its p-type doping concentration drops back to that of the substrate region 34 at about 3.5 µm below the surface 14.

The pH network 44 is connected to the surface 14 through a number of low resistivity p + regions 46 extending along the columns in the programmable read memory. The insulating region 16 and buried network 44 in combination with the connection regions 46 laterally isolate cells 12 of a given 15 n + region 32 electrically from cells 12 of all other n + regions 32. Thereby this combination laterally isolates the rows from each other . The network 44, together with the connection region and 46, also forms a path of low resistance for draining holes which are received by the parasitic npn collector region 34 during the part-programming. This serves to further prevent the programming one of cells 12 damages the programmable diodes in other cells 12 along the same column.

Each buried area 32 is separated laterally from the buried network 44 by an associated layer doped area consisting of the p-type substrate area 34 and a corresponding n area 48 located between the area 34 and the bottom surface. of the oxide region 16. The n regions 48 each have a relatively uniform net dopant concentration of about 8. 10 3 atoms / cm. The low-doped combination of the p region 34 and the n regions 48 ensures that the insulating substrate transitions 36 have a sufficiently high breakdown voltage (typically about 30 Vj.

The programmable read memory is completed by a configuration of conductors in contact with the various monocrystalline regions extending up to the top surface 14. On each p + region 46, an 8301234 PHA 1067 15 layer 50 of platinum nickel silicide is deposited. a layer 52 of titanium-tungsten. On the n + regions 28 and hZ along the surface 14 and on the titanium-tungsten regions 52 there is a pattern of conductors consisting of aluminum with about 1 silicon. The conductors and are column conductors. With the exception of the guide 54 ^ and its counterparts, which form a connection to the row guides, they extend. all other conductors 5 ^ -Qt as shown with conductor iu Fig. 2b, along the 10 columns.

A second crossing path of conductors of conventional design is used to form the row conductors and complete the configuration of conductors. This second intersecting pattern of conductors is not shown in the drawing for clarity. When using the second pattern of conductors, a layer of phosphorus-doped silicon dioxide (Vapox) lies on the conductors and the portion of the oxide region 16 between the conductors 5 ^ ·· The intersecting pattern of conductors consists of pure aluminum, which is located on the Vapox layer and is connected to the conductor and its counterparts by means of aluminum filled vias extending through the Vapox layer.

To program the programmable read memory, a blocking current of about 40 mA is forced through each pn junction 30 to be destroyed. Vaaneer e.g. the junction 30β must be destroyed, an appropriate reverse voltage is applied between conductors 5 ^ · «and * ^ 5 ^ -q for an appropriate time, which is typically less than 1 ^ usec, to cause avalanche breakdown in the programmable diode and to generate the specified reverse current. This heats the programmable diode until the eutectic temperature of aluminum silicon of about 577 ° C is reached. At this point, the programmable diode is permanently shorted as aluminum migrates from the conductor 5 ^ through the n + region 28 ^ to establish an ohmic contact with the p region 22 ^. Therefore, depending on the convention used, 8301234 PHA 1067 '16 places a logic "0" or a logic "1" in cell 12 ^, while cells 12, whose programmable diodes remain intact, are in the opposite logic state are located.

Figures 3a-3n show stages in the manufacture of the programmable read memory of Figures 1, 2a and 2b. In the manufacturing process, boron is used as the n-type impurity to form the various p-type regions. Unless otherwise indicated, boron is applied by ion implantation. Phosphorus, arsenic and antimony are optionally used as the complementary n-type dopants. Unless otherwise specified, they are also applied by ion implantation. Other suitable impurities can be used in place of these dopants. Many of the ion implantation steps can also be replaced by diffusion steps.

Conventional cleaning and photoresist masking techniques are employed in forming the various insulating, p-type and n-type regions. To simplify discussion, references to the cleaning steps, the photoresist mask making steps and other known semiconductor thnology steps are omitted from the following description. Unless otherwise indicated, each silicon dioxide etching is carried out with a buffered etchant consisting of about 7 parts of 40% fo ammonium fluoride and 1 part kS% fluorohydric acid.

The preliminary steps in the process consist of defining the location for the composite buried layer, which consists of the n + regions 32 and the f p + network 44. In FIG. 4a, a semiconductor body comprising a p-type monocrystalline silicon substrate 60 with a resistivity of 7-21 cm -1 and a thickness of about 500 µm is started from. The body is exposed to an oxidizing atmosphere of oxygen and hydrogen at 1000 ° C for 360 minutes, around a layer 62 of silicon dioxide with a thickness of about 1.2 µm on 8301234 PHA IO67 1? grow the top surface of the substrate 60. A photoresist mask 64 with openings above the locations designated for the areas 32 and the network 44 is formed on the oxide layer 62. The exposed portions of the oxide layer 62 are etched for 18 minutes until a layer of silicon dioxide 80-140 nanometers thick remains in the open places in the mask 64.

After the mask 64 has been removed, a non-critical photoresist mask 66 having a nominal thickness of 10 700 nanometers and with openings above the areas intended for the regions 32 is formed on the surface of the body, as shown in FIG. 3t> · The exposed parts of the remaining part of the oxide layer 62 are etched for 3 minutes to remove the silicon in the substrate 60.

15 to uncover. When the mask 66 is in its position 1 5, antimony becomes at a dose of 2. 10 D ions / 2 cm and with an energy of 50 keV implanted through the gaps in the remainder of the oxide layer 62 to form n + regions 68.

After the mask 66 is removed, the semiconductor body is exposed to nitrogen at 1000 ° C for 20 minutes, oxygen and hydrogen at 1000 ° C for 13 minutes, and nitrogen at 1200 ° C for 75 minutes, to expose recording levels 70 to the exposed 25 formed regions of the substrate 60 by growing layers 72 of silicon dioxide with a thickness of about 240 nanometers. The high temperature of this step also drives the antimony in regions 68 further down (and sideways) into the substrate 60. A non-critical photoresist mask 74 with a nominal thickness of 1.2 µm and a network above the furrow. the buried network 44 designated location located opening is formed on the surface. The exposed parts of the remaining part of the oxide layer 62 are etched onto the silicon in the substrate 60 for 3 5 minutes. When the mask 74 is in place, boron is implanted into the substrate 60 at a dose of 2.10 2 ions / cm and with an energy of 18 KEY to form the p + regions 76.

830 1 23 4 PHA 1067 18

After the mask 74 is removed, the semiconductor body is etched for 20 minutes to remove the oxide layer 72 and the remaining parts of the oxide layer 62, as shown in FIG. 3d is shown. An arsenic-doped epitaxial layer 78 with a resistivity of about 0.7 cm is grown to a thickness of about 1> 75 µm on the exposed silicon surface. The areas 68 and 76 are thus buried in the structure.

The oxide region 16 is now being formed. A layer of silicon dioxide of about 30 nanometers thick is first grown on the surface of the epitaxial layer 78. This is done by exposing the body to dry oxygen at 1000 ° C for 11 minutes.

A silicon nitride layer 82 having a thickness of about 120 nanometers is applied to the oxide layer 80 by a conventional low pressure chemical vapor deposition process. The body is then exposed to oxygen and hydrogen at 1000 ° C for 120 minutes to form a thin layer 84 of silicon dioxide on the nitride layer .82. As shown in FIG. 3, each recording floor 70 returns to layers 78, 80, 82, and 84. A photoresist mask 86 with a network aperture corresponding to the location for the insulating region 16 is formed on the oxide layer 84. The exposed portion of the oxide layer 84 is removed by etching for 1.5 minutes.

After the mask 86 is removed, the exposed portion of the nitride layer 82 up to the oxide layer 80 is removed (see Fig. 3e) by etching with hot phosphoric acid at 165 ° C for 50 minutes. The exposed portion of the oxide layer 80 is then removed to epitaxial layer 78 by etching for 1 minute. In the exposed portion of the epitaxial layer 78, a depression 87 is etched over approximately 650 nanometers. This takes place for 5 minutes at 23 ° C using an etching agent consisting of 250 parts of 70% nitric acid, 40 parts of 49% hydrofluoric acid and 1000 parts of acetic acid saturated with iodine.

The insulating region 16 with a thickness of approx.

8301254 PHA 1067 19 1.25 ^ tun is now formed in the recess 87 as shown in FIG. 3f, by exposing the body to oxygen and hydrogen at 1000 ° C for 360 minutes. The oxide region 16 does not extend into the substrate 60, so that portions 48 of the n-type epitaxial layer 78 lie directly below the lower surface of the oxide region 16. During this high temperature step, the boron in the region 76 diffuses both down into the substrate 60 and up into the epitaxial layer 78 to form the p + network 10 44, which extends up the side walls of the region 16 extends. Also, the antimony in regions 68 diffuses slightly down into the substrate 60 and slightly up into the epitaxial layer 78 to form the n + type buried regions 32. In particular, the parts of the lower surface of the oxide region 16 above the n + regions 32 are approximately 100 nanometers lower than the remainder of the lower surface of the region due to the recording floors 70. The buried regions 32 extend at least far enough upwards that it touches the lowest surface part of the region 16.

The remaining n-type portions of the epitaxial layer 78 adjacent laterally to the oxide region 16 are used for cells 12 and junction areas 38 and 46. Each of these n-type monocrystalline portions intended for cells 12 has under the bird's pelvis 18 dimensions of approx.

2yum x 2yum.

The remaining parts of the oxide layer 84 (which grow slightly during the previous step at high temperature) are, as in Pig. 3S is indicated, removed by etching for 1.5 minutes. The remaining parts of the nitride layer 82 are also removed by etching with hot phosphoric acid at 165 ° C for 35 minutes.

The remaining parts of the oxide layer 80 are also removed by etching for 1 minute. An electrically insulating layer 88 of silicon dioxide with a thickness of approx.

1000 µl is grown along the exposed parts of the egg epitaxial layer 78 by exposing the wafer to oxygen and hydrogen at 900 ° C for 26 minutes. Since this oxidation takes place at a relatively low temperature, no appreciable redistribution of the contaminants in the areas 32 and the network 44 occurs. The formation of the buried areas 32 and the buried network 44 is hereinafter · largely ready.

The terminal regions 38 and 46 as well as any transistors in the peripheral circuit are now provided. A non-critical photoresist mask 90 with a nominal thickness of about 800 nanometers and openings above the locations designated for the connection areas 38 is formed on the surface. The exposed parts of the oxide layer 88 are removed by etching for 2 minutes. When the mask 90 is in place, phosphorus at a dose of 3 * 10 ions / cm and with an energy of ^ 180 KEV is introduced into the exposed parts of the epitaxial layer 78 implanted to form n + regions 92.

After the mask 90 is removed, the semiconductor body is fired in nitrogen at 1000 ° C for 120 minutes to repair grating damage.

Then it is exposed to oxygen and hydrogen at 900 ° C for 31 minutes to grow layers 94 of silicon dioxide of about 140 nanometers thick at the exposed portions of the epitaxial layer 78, as shown in FIG. . 3b. During this oxidation step, the thickness of the oxide layers 88 increases by ca.

Nan00 nanometer. As a result, the phosphorus in regions 92 undergoes redistribution such that it diffuses downwards, while the boron in network 44 diffuses slightly upwards. During these treatments, no significant redistribution of the antimony occurs in regions 32.

A photoresist mask 96 with a nominal thickness of 1.2 µm and with windows above the locations intended for p + terminal areas 46 is now applied to the surface. The mask 96 is non-critical to the regions 46. When the mask 96 is in place, boron is double implanted through the exposed portions of the oxide layer 88 into the portions of the epitaxial 8301234 EHA 1067 21 t beneath it. layer J8 to form the p + regions 98. The first implantation takes place with a dose of 1.10 ions / cm and with an energy of 180 KEV, while the second implantation takes place with a dose of 1.5 · 10 ions / cm and takes place with an energy of 75 KEV. The double boron implantation also establishes a desired impurity distribution for the bases of npn transistors and for the emitters and collectors of pnp transistors in the peripheral circuit.

After the mask 96 is removed, a photoresist mask 100 having a nominal thickness of 8000 and with apertures above the locations for the connection areas 38 is applied to the surface, as shown in FIG. 3i · The mask 100 is non-critical to areas 38. The oxide layers are removed by etching for 4 minutes. n + regions 42 are formed in the upper parts of regions 92, 15 by first implanting deep arsenic at a dose of 1.10 ions / 2 cm and at an energy of 180 KEV, removing the mask 100 and. then shallow arsenic at a dose of 2. 10 ions / cm and implant with an energy of 50 KEV. The dual arsenic implantation also establishes a desired impurity distribution for the 25 emitters of npn transistors in the peripheral circuit.

The semiconductor body is fired in nitrogen at 1000 ° C for 60 minutes to repair implantation lattice damage and to accomplish redistribution of the arsenic and boron in regions 42 and 98. As shown in FIG. 3j, the areas 42 extend downward. The boron in the buried network 44 expands slightly outward and the regions 98 expand downward 35 and join the network 44. This creates the p + terminal regions 46. The regions 32 and 92 also grow somewhat.

Then the diodes in cells 12 are formed 8301234 PHA 1067 22. A non-critical photoresist mask 102 having a nominal thickness of 1.2 µm and with openings above the locations for the cells 12 is formed on the surface of the semiconductor body. The exposed portions of the oxide layers 88 are removed up to the epitaxial layer 78 by etching for 5 minutes. When the mask 102 is in place, boron in the epi-

taxial layer 78 implanted at a dose of 3.5 · 10 J.

2 ions / cm and with an energy of 110 KEV, to define the pn-over-10 corridors 26. Arsenic is then similarly implanted into the epitaxial layer 78 at a dose of 6.10 ions / cm and with an energy of 50 KEV to define the pn junctions 30. In each of these implants, the insulating region 16 serves as a mask 15 to control the lateral spread of the boron and arsenic impurities and thereby the lateral extent of the transitions 26 and 30. Both of these implants lead to the formation of the p areas 22 and the n + areas 28.

After the mask 102 is removed, the semiconductor body is fired at 950 ° C in nitrogen for 5 minutes, in oxygen for 23 minutes and then in nitrogen, also for 5 minutes, to repair the lattice damage caused by the implantations to form regions 22 and 28. This tempering causes regions 22 and 28 to expand slightly downward to their final positions, as shown in FIG. 3h, leaving the regions 20 as the remaining parts of the n-type epitaxial layer 78 within the cells 12. Areas 42 and 92 also extend slightly downward to their final positions, the areas 92 becoming n + areas 20 joining the associated buried areas 28. Areas 46 also extend slightly downward to their final positions. During the firing treatment, layers 104 of silicon dioxide having a thickness of about 40 nanometers grow on the surface at the area of the exposed silicon of the areas 8301234 PHA. 1067 23 28 and 42. This temperature treatment completes the manufacture of the diodes in the PROM cells 12 as well as the connection areas 38 and 46.

Fig. 4 shows the final doping concentration as a function of the depth of the plane 14 (which lies below the oxide layer 104) in the center of each cell 12 into the corresponding n + region 32. FIG. 4 is e.g. drawn according to plane 2b-2b in Fig. 2a or the equivalent plane in FIG. 3k · The asterisked reference marks in FIG. 4 refer to the doping concentrations and name locations of the transitions of the corresponding PROM elements designated by these numbers. As shown in Fig. 4, the maximum boron concentration in each p region 22 occurs approximately midway between its pn junctions 26 and 30 in their final positions.

The body is now ready to manufacture the conductive connections that contact areas 28, 42 and 46. A non-critical photoresist mask 106 with 20 openings above p + regions 46 is applied to the surface. Oxide regions 88 are removed to regions 46 by etching for 4 minutes.

After the mask 106 is removed, about 25 nanometers of platinum with 60 nickel is deposited on the surface by conventional sputtering techniques. The whole is then sintered at 475 ° C to convert the platinum-nickel deposited on the exposed silicon of the bonding regions 46 into layers 50 of platinum-nickel silicide, as shown in FIG. 3rd is shown.

The platinum-nickel not converted into silicide is removed by etching with king water. A layer of titanium tungsten with a thickness of about 100 nanometers is deposited on the surface thus obtained. An aluminum layer with a thickness of about 100 nanometers is then precipitated. A photoresist mask 108, the polymerized photoresist of which generally lies on regions 46, is formed on the surface of the body. The exposed aluminum is removed by etching with 8301234

, T

r "γ · ΡΗΔ 1067 24 a common aluminum etchant, leaving aluminum regions 110, while the resulting exposed titanium tungsten is etched with hydrogen peroxide, leaving titanium tungsten layers 52.

After the mask 108 is removed, a non-critical photoresist mask 112 is formed on the surface with polymerized photoresist disposed on the composite sandwich structures of regions 50, 52 and 110, as shown in FIG. 3m is shown. The oxide layers 104 are removed by etching for 1.7 minutes with a buffered etchant consisting of 20 parts of k0 ° / o ammonium fluoride and 1 part of h2 ° / o or some acid acid to expose the n + regions 28 and 42 .

After the mask 112 is removed, the aluminum layers 110 are removed by etching. A layer of aluminum with 1 ° / o silicon is now deposited on the surface to a thickness of 700 nanometers. The aluminum layer is patterned to provide conductors by forming a photoresist mask 114 on the aluminum layer with polymerized photoresist located in regions 28 and 42 and then removing the exposed aluminum by etching with a standard aluminum etchant, as in fig. 3n is shown. Then, the mask 114 is removed and the structure of FIG. 2a 25 (and Fig. 2b) is obtained.

As explained above, a second layer of aluminum conductors is applied in the usual manner. This is done by depositing a Vapox layer on the surface to a thickness of approximately 900 nanometers etching 30 vias onto selected conductors of the conductors 54, otherwise using a suitable photoresist mask, a layer of pure aluminum on the Vapox layer and on the selected depositing conductors and then patterning the aluminum layer using another photoresist mask to complete the programmable read memory.

Although the invention has been described by way of special embodiments, this description is 8301234 r PHA. 1067 are given by way of example only and in no way limit the scope of the invention. The connection areas for the composite buried layer would e.g. can be applied after the diodes have been placed in the PROM-5 cells. Also, the bonding areas for the composite buried layer and the diodes for the PROM cells could be applied using substantially the same implantation and diffusion steps. Opposite conductivity-type materials and dopants may be used in place of the materials and dopants described above. Thus, within the scope of the invention, various variations can be chosen by the skilled person.

15 20 25 30 35 8 301 234

Claims (23)

1, Programmable read memory (PROM) in a semiconductor body having a recessed electrical insulating region on a first surface and an adjoining single crystalline semiconductor region, with a plurality of laterally separated memory cells along the surface 5, wherein each cell has a substantially horizontal first pn junction, located in the semiconductor region, and has a corresponding second pn junction, which together form a pair of pn junction diodes connected against each other, characterized in that each second pn junction is substantially horizontal and located above the corresponding first pn junction such that the intermediate region common to each pair of diodes between the pn junctions is completely bounded by the insulating region. Programmable read memory according to claim 1, characterized in that every second pn junction is located in the semiconductor region. Programmable read memory according to claim 2, characterized in that the maximum of the net dopant concentration in each intermediate region is below the second pn junction. Programmable read memory according to claim 3, characterized in that the maximum net dopant concentration in each intermediate region between the second pn junctions is at a vertical distance from the plane midway between the two pn junctions, which is not greater than 20 ° / o of the distance between the two pn junctions. Programmable read memory according to claim 1, 2, 3 or 4, characterized in that each first pn junction 30 is a matrix element and each second pn junction is a programmable element. Programmable reading memory according to claim 5, characterized in that the insulating region consists of oxidized semiconductor material. 35 Programmable reading memory according to claim 1, 2 or 3) wherein the upper limit of a lower region of a first conductivity type in each cell with the intermediate region forms the first pn junction, characterized in that 8301234 ·· ♦ PHN 1067 27 the semiconductor body includes a plurality of doped buried regions of the first conductivity type which are laterally separated from each other and which each belong to at least one of the lower regions and form a continuous unit with each associated lower region and along the entire circumference of each associated lower region adjacent to the insulating area. 8. Programmable reading memory according to claim 7j, characterized in that the average net dopant concentration in the buried areas is at least two orders of magnitude higher than the average net dopant concentration in the lower areas. Programmable read memory according to claim 8, characterized in that the semiconductor body for each buried area comprises a first conductivity type connection region extending from the buried region to the surface. 10. Programmable reading memory according to claim 11, characterized in that the semiconductor body is provided with a buried network of a second conduction type opposite to the first conduction type, which laterally surrounds each buried area. 11. Programmable reading memory according to claim 12, characterized in that the semiconductor body is provided with a layer of doped area, which connects to the buried areas and the buried network and extends upwards along their entire lateral circumference to the insulating area, separate the buried network and the buried areas. Programmable reading memory according to claim 11, characterized in that the average net doping concentration in the buried network and the buried areas is at least one order of magnitude higher than the average net doping concentration in the low-doped area. 35 Programmable read memory according to claim 12, characterized in that the semiconductor body comprises at least one second conductivity type connection region, which extends from the buried network to the surface 8301234 PHN 1067 28. 14. A method of manufacturing a programmable read memory according to claim 2, characterized in that at least one of the two pn junctions is obtained by doping the semiconductor body with a dopant via the surface of the semiconductor body the insulating area being used as a mask. 15. A method according to claim 14, characterized in that the doping is effected by ion implantation with an energy sufficient to cause the maximum concentration of the dopant in each intermediate region to be between the two pn junctions. 16. A method according to claim 14, characterized in that the ion implantation takes place with an energy sufficient to cause the maximum concentration of the dopant to occur in each intermediate region between the two pn junctions at a vertical position. bare distance from the center point between the two pn junctions, not exceeding 20 ° / o of the distance between the two pn junctions. 17. A method according to claim 16, characterized in that after doping the semiconductor body is fired at a suitable temperature to restore lattice damage, without significant redistribution of semiconductive impurities in the programmable read memory. Method of manufacturing a programmable readable memory according to claim 7, characterized in that a plurality of buried regions of the first conductivity type are formed which are laterally separated from each other in the body and have an average net dopant concentration. higher than that of the lower 35 regions, each buried region associated with at least one of the lower regions forming a continuous unit upwardly with each associated lower region and along the entire circumference of each associated lower 8301234 «*» PHtf 1067 29 area is adjacent to the insulating area. Method according to claim 18, characterized in that the steps for forming the buried areas and applying the insulating area together comprise: selectively applying a contaminant causing the first conductivity type in a single crystal line semiconductor sub street of the second conductivity type at the same number of first places separated from each other at the surface of the substrate; growing an epitaxial semiconductor layer on the surface of the substrate; removing a network-shaped portion of the epitaxial layer along the surface to form a depression in the IS semiconductor body and selectively exposing the substrate and the remaining portion of the epitaxial layer to an oxidizing atmosphere at high temperature , to oxidize a portion of the epitaxial layer along the depression, to form the insulating region, and to cause some of the contamination of the first conductivity type to diffuse up into the epitaxial layer so far that the insulating region extends to in the buried areas. 20. A method according to claim 19, characterized in that a buried network of the second conduction type is formed, which laterally surrounds each buried area and has an average net doping concentration higher than that in the remaining part of the substrate 30 of the second conductivity type. 21. A method according to claim 20, characterized in that the buried network is formed by selectively applying a contaminant causing the second conductivity type in the substrate to a second location laterally, before the epitaxial layer has grown. surrounding places and separated from them. 22. A method according to claim 29, characterized in that a portion of the impurity causing the second 8301234 PHN 1067 conductivity type diffuses upwards in the epitaxial layer during the formation of the buried network. The method according to claim 22, characterized in that the semiconductive impurities deposited at the first and second places in the substrate are far enough apart to keep the buried areas separate from the buried network. 10 15 20 25 35 8 301 234