JPH0618256B2 - Programmable semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates generally to semiconductor programmable read-only memories (PROMs), and more particularly to a pair of diodes with each PROM cell facing each other (one of the diodes being selectively destroyed to produce a memory. Can be programmed).

Background Art PROMs are becoming increasingly important in field-programmable electronic memory applications. A PROM of the type including a row and column array of memory cells each consisting of a pair of back-to-back PN junction diodes.
Is very important. The first diode of the diodes of each cell acts as an array element for electrically isolating the cells, while the second diode selectively selects to program a logic "0" or a logic "1" into the cell. Can be destroyed. A programmable diode is destroyed by applying a sufficiently high reverse current to its PN junction and permanently shorting this junction.

In some prior art PROMs using back-to-back diode structures, an electrically insulating material such as silicon dioxide is used to laterally separate the memory cells. GB 2005079 "Programmable Read Only Memory Cell" discloses a PROM as follows. According to this PROM, each array diode is a vertical diode and its PN junction lies horizontally in the monocrystalline silicon region of the semiconductor body and completely laterally in the deep region of silicon dioxide in the semiconductor body. It is adjacent. Each programmable diode is a horizontal diode and its PN junction in the region of polycrystalline silicon is adjacent to the single crystal region along its upper surface. PN of each programmable diode
The junction generally extends perpendicular to the lower surface of the semiconductor body. This PROM has N-type on the upper surface of the P-type substrate.
Manufactured by forming a P-type epitaxial layer and forming a P-type epitaxial layer on the N-type epitaxial layer. The deep N-type region contacts the bottom surface of the deep oxide region formed around the epitaxial layer portion to form the array diode. Each cell is provided with an opening through the insulating layer that covers the P-type epitaxial layer. The PN junction for the programmable diode is formed in a layer of polycrystalline silicon deposited on the insulating layer and on the portion of the P type epitaxial layer exposed by the opening.

Although a relatively small current of about 20 mA is required to program this PROM, the horizontal diode increases cell area. Furthermore, during fabrication, the characteristics of the PN junction in polycrystalline silicon can be determined by
It is less controllable than bonding.

T. Fukushima et al., European Patent No. 001817.
No. 3, "Programmable Read Only Device" discloses another such PROM. In each memory cell of this PROM, the PN junctions of both diodes are provided in the single crystal silicon region. An isolation region containing silicon dioxide directly adjacent to the single crystal region separates the cells. Each PN junction is approximately horizontal in the middle of the cell and extends to the upper surface of the single crystal region at a location spaced from the sidewalls of the isolation region. The PN junction of each array diode has a corresponding programmable
It surrounds the PN junction of the diode laterally and upwards. The PROM is manufactured by selectively forming an N-type tub along the upper surface of a P-type silicon substrate and then forming an N-type epitaxial layer on the upper substrate surface. A lateral isolation region is then formed, a P-type region is formed in the epitaxial layer on the tub, and an N-type region is formed in the P-type region to produce a PN junction pair.

In this PROM, shallow regions can be used to form the diodes, but incorporating diodes in each cell significantly increases cell area due to photolithographic array intersections. The memory elements occupy an area of about 9 square microns. Therefore, the programming current is increased. In addition, the parasitic transistor behavior in programming the cells in one tab forward biases the PN junction between the substrate and other tabs along the same column with respect to the tab, and Damage the programmable diode of the cell in the tab.

DISCLOSURE OF THE INVENTION A PROM formed in a semiconductor body having an electrically insulating region preferably adjacent to a semiconductor oxide and an adjacent single crystal semiconductor region is laterally separated from each other along an upper surface of the semiconductor region. It has a group of PROM cells. Each cell has a substantially horizontal first PN junction in the semiconductor region and a corresponding second PN junction. These PN junctions form a pair of PN junction diodes having mutually opposite forms. Each second PN junction is substantially horizontal and is provided on the corresponding first PN junction as follows. That is, the intermediate cell region between each pair of PN junctions is completely adjacent to the insulating region. Each second PN junction is preferably provided in the semiconductor region.

The "near horizontal" applied to the PN junction of the cell is
It means that each of these PN junctions is mostly present in a plane parallel to the substantially flat bottom surface of the semiconductor body.
Each junction is "almost horizontal", even though the PN junction may curve slightly upward (or downward) where it is adjacent to the insulating region. Thus, both diodes in each PROM cell are vertical diodes. 1st P
The lower diode formed by the N-junction is the array element, while the upper diode formed by the second PN junction is the programmable element. By having the PN junction in each cell completely adjacent to the isolation region, this PROM occupies a very small space. The memory elements in each cell typically occupy an area of about 2.25 square microns, which is much smaller than in comparable prior art devices.

The maximum dopant concentration in each intermediate region should occur midway between the PN junctions of the pair, optimally near the midpoint between the PN junctions of the pair. This dopant state achieved by the ion implantation method facilitates PROM fabrication and improves programming operation.

The lower cell region just below the first PN junction is of the first conductivity type and the intermediate cell region is of the opposite second conductivity type. The cell is
Usually, it is formed above the substrate region of the second conductivity type.
This creates the following potential problems. That is, the substrate region acts as the collector of the parasitic transistor, the lower region of each cell acts as the base, and the adjacent intermediate cell acts as the emitter. When the second PN junction of this cell is destroyed, its first PN junction becomes forward biased, which turns on the associated parasitic transistor. The current injected by the parasitic transistor into the substrate region causes a significant voltage there to forward bias the PN junction between the substrate region and the lower cell region of the other cells along the same column. Like This may deteriorate the second PN junctions of these other cells and change the diode characteristics of these other cells.

Appropriate use of composite buried layers alleviates this problem, and
An intermediate electrical connection to the lower cell area can be provided.
The buried layer has a plurality of highly-doped buried regions of the first conductivity type immediately below the lower cell region. Each buried region is adjacent to an insulating region along the entire lower edge of each lateral perimeter of one or more associated lower cell regions. By contacting the buried region with the insulating region, the gain of each parasitic transistor can be reduced, typically to 1/100. As a result, the voltage developed in the substrate area during programming of one cell can be significantly reduced, protecting programmable diodes in other cells along the same column.

The composite buried layer has a second conductivity type highly doped buried web laterally surrounding each buried region. This buried web provides a low resistance path that removes charge carriers injected into the substrate region by parasitic transistors during programming, further preventing the substrate potential from rising.

The buried web is laterally separated from the buried region by a lightly doped region that includes the substrate region and extends to the insulating region. This lightly doped region serves to increase the breakdown voltage of the substrate PN junction to an acceptable value.

An important advantage of this memory is that it is insensitive to many material defects and defects that occur during the process. Only the area of the actual memory element of each cell is subject to such defects, which area is very small. Connections that extend through the insulating layer to the composite buried layer are less sensitive to many of these defects,
Many of the PN junctions are partially or wholly protected by the insulating region. Therefore, this PROM is very suitable for the production of very large memory arrays.

In manufacturing a PROM, first, an insulating region is formed as follows. That is, the insulating region is completely adjacent to each lateral boundary of each of the group of single crystal portions of the doped region of the first conductivity type spaced from each other along the top of the doped region. A second conductivity type dopant is introduced into the single crystal portion through the top surface to form a first PN junction. A second PN junction can be formed by similarly introducing a dopant of the first conductivity type into each single crystal portion via the top surface. It is preferable to use the insulating region as a mask to control the lateral spread of these dopants within each single crystal portion. The second conductivity type dopant is ion-implanted, and the PROM is annealed at a sufficiently low temperature to form a PR.
Lattice defects due to the introduction of dopants can be repaired without significant redistribution of the dopants or other impurities originally introduced into the OM.

The composite buried layer and insulating region are typically formed at an early stage of PROM fabrication. Impurities of the first conductivity type are selectively introduced into the single crystal semiconductor substrate of the second conductivity type at a plurality of first positions separated from each other along the surface of the substrate to arrange the buried layer. A buried web is also provided by selectively introducing impurities of a second conductivity type into the substrate at second positions laterally surrounding each of the first positions and spaced from each of the first positions. It is preferable to arrange it at. Next, an epitaxial semiconductor layer is grown on the surface of the substrate. The web-like portion of the epitaxial layer is removed along its upper surface to form a groove. Next, the substrate and the remaining portion of the epitaxial layer are selectively placed in a high temperature oxidizing atmosphere to oxidize the epitaxial layer portion along the groove to form an insulating region, and to remove impurities introduced into the substrate. A portion is diffused upward in the epitaxial layer to form a composite buried layer.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a cross-sectional array of a preferred embodiment of a PROM which includes a group of identical PROM cells each consisting of a pair of back-to-back oxide wall vertical diodes. 2a
FIGS. 2 and 2b are cross-sectional views of the embodiment of FIG. 1 perpendicular to one another, showing P in a semiconductor body with a flat bottom 10.
The structure of ROM is shown. As shown in FIGS. 2a and 2b, the cross section of FIG. 1 is a plane 1-1 parallel to the bottom surface 10. The elements shown in phantom in FIG. 1 are below surface 1-1. The terms “bottom”, “bottom”, “top”, “top”, “bottom”, “top”, “vertical”, “horizontal”, “lateral” refer to when the surface 10 is parallel to the ground. It is defined for convenience with respect to the orientation of the semiconductor body.

The PROM cells are arranged in rows and columns. The line is
About 20 microns apart.

6 PROM cells 12 _B , 12 _D , 12 _F , 1
2 _B ′, 12 _D ′, 12 _F ′ are shown in FIG. Cell 1
2 _B , 12 _D , 12 _F are in one row, and cell 1
2 _B ′, 12 _D ′, 12 _F ′ are in adjacent rows. Thus, each subscript "B", "D", or "F" indicates an individual column, unmarked numbers indicate rows shown in Figure 2a, and dashed numbers indicate Shows adjacent rows. Some of the inter-row areas and the areas located in the center on these inter-row areas are designated by the corresponding subscript "A",
It is indicated by a reference numeral including "C", "E", and "G". Cells 12 _B , 12 _D , 12 _F , 12 _B ′, 1 distinguished by subscripts “B”, “D”, or “F”
2 _D ′, 12 _F ′, those elements, or any one of the separate column elements, or the reference signs are subscripts “A”, “C”,
For any of the areas including "E" and "G", the subscripts "A" to "G" and the reference signs with dashes are shown as complete reference signs in the drawings. In these descriptions, these subscripts and dashes are almost omitted.
Moreover, some elements of cell 12 are not shown or only partially shown to avoid over-representation. For example, only the elements of cell 12 _D are shown in FIGS. 2a and 2b.
It is shown completely in the figure.

A cell 12 is formed in a doped single crystal silicon region of the body along an upper surface 14 of this region, the cell being a web of silicon dioxide that is selectively submerged along the surface 14 into the body. It is laterally separated from each other by adjacent portions of the electrically insulating region 16. The single crystal region in FIGS. 2a and 2b is the portion between the surfaces 10 and 14 excluding the insulating region 16. The center-to-center distance of the oxide isolation region 16 portions on either side of the cell 12 along the row is about 11 microns. Oxide region 16
Has a bird's beak 18. This portion penetrates into the single crystal region, narrowing each cell 12 along the surface 14 to a cross-sectional area of approximately 2.25 square microns. The bottommost surface of oxide region 16 is about 1.1 microns into the body, measured from top surface 14.

Each cell 12 is composed of a lower array diode and an upper programmable diode. The array diode is a vertical PN junction element formed by the lower N region 20 and the intermediate P region 22. These common interfaces have a lateral area of about 4 square microns and about 16
Form a first PN junction 26 having a breakdown voltage of volts. The programmable diode is a vertical PN junction element consisting of a P region 22 and an upper N ⁺ region 28. These common interfaces have a second PN junction 30 having a lateral area of about 3 square microns and a breakdown voltage of about 6 volts.
Is. The difference in junction area is due to the large penetration of bird's beak 18 into cell 12 along junction 30. The larger area of the junction 26 serves to prevent the junction 26 from degrading when the programmable diode is programmed.

P region 22 is completely adjacent to the sidewall of insulating region 16 so that PN junctions 26 and 30 are also completely adjacent to that sidewall. Each PN junction 26 or 30 has a majority of its extent horizontal, but generally bends up near the sidewalls of the oxide region 16. The center of each joint 26 or 30 is parallel to the lower surface 10 and there are very few portions of the joint 26 or 30 that bend upwards so that
It can be said that the joints 26 and 30 are "almost horizontal".

As will be described in detail below, the maximum concentration of P-type dopant in P region 22 occurs between junctions 26 and 30 (rather than along junction 30). Maximum P-type concentration is in the middle region 2
The location present in 2 is preferably at a vertical distance of less than 20% of the distance between junctions 26 and 30 from the midpoint between junctions 26 and 30. Maximum P type concentration is junction 2
Optimally, it occurs approximately midway between 6 and 30.
Regions 20, 22, and 28 may be structurally considered as NPN transistors having a permanently floating (not connected) base, but are not operationally transistors. The reason is that using such a dopant distribution makes the possible transistor operation very inefficient. This is because the intermediate region 22 is wider than the base of a normal transistor, which results in a very small current gain (about 2). Moreover, this dopant distribution facilitates the fabrication of PROMs in large arrays. The reason is that the high P along the sidewall of the oxide region 16
The presence of the topographical dopant concentration reduces the likelihood of short circuits due to inversion paths or other defect mechanisms.

The cell 12 is formed as the upper part of the structure in which an electrical connection must be provided between the lower N region 20 and the PROM row line. The lower part of this structure is composed of a lightly doped P-type semiconductor substrate. Each P region 22 acts as an emitter of a vertical parasitic PNP transistor in the absence of a buried layer having very heavily doped N and P regions, described below. The base of this transistor is the adjacent N region 20 and its collector is the remaining lightly doped P-type portion of the substrate.

When programming a cell, all N's along an individual column
⁺ Potential region 28 is increased by increasing the potential of the connected column lines to these N ⁺ regions 28. When any particular cell 12, such as cell 12 _D , is programmed, its PN junction 30 _D avalanches to its P region 22 _D and its PN junction forward biased. forcing current flow through 26 _D. Parasitic PNP Thereby, associated with the cell 12 _D
The transistor can be turned on. The base-collector junction of this vertical parasitic transistor is the base-emitter junction of the lateral parasitic NPN transistor.
The base-collector junction of this NPN transistor is the cell 1 along the same column as the rest of the lightly doped P-type substrate.
_2D 'and any other N region 20 of the cell 12.

When the parasitic PNP transistor saturates, its base-collector junction is forward biased, raising the substrate voltage and turning on the lateral parasitic NPN transistor. This allows the voltage of the N-region 20 _D 'N region 20 _D
The voltage may be reduced to a voltage close to that of PN junction 30 _D ′, which may deteriorate the PN junction 30 _D ′. The reason is that the N ⁺ region 28 _D ′ is N
^This is because it is at the same potential as the ⁺ region 28 _D. in short,
The action of the parasitic PNP transistor associated with each cell 12 being programmed can damage the programmable diodes of other cells 12 along the same column. The use of a composite buried layer with cells 12 in accordance with the present invention alleviates this problem and provides intermediate electrical connection to the wordlines and electrical isolation between the rows.

A portion of this composite buried layer is formed by a set of buried N ⁺ regions 32 that are immediately below the lower N region 20 and contact the lower surface of the oxide region 16. It is particularly preferred that each embedding region [or tub] 32 be contiguous with four of the lower regions 20. However, in order to simplify the drawing, the first
In FIGS. 2a and 2b, each tab 32 is shown as being continuous with only two of the lower regions 20. For example, the buried region 32 _C may be replaced by the lower regions 20 _B and 20 _D.
To be continuous. As a result, the individual tabs 32 abut the insulating region 16 along the entire lower edge of the lateral perimeter of each lower region 20 that is continuous with the individual tab 32.

The average net dopant concentration in the buried region 32 is about 1.6.
× 10 ¹⁸ atoms / cm ³ . The lower area 20 is approximately 8 × 1
It has a relatively uniform net dopant concentration of 0 ¹⁵ atoms / cm ³ . This means that the dopant concentration in tub 32 decreases upward along oxide region 16 to the dopant concentration in region 20 where it abuts region 20 about 1.0 micron below surface 14. It means that. The bottom of the buried region 32 extends into the body about 4 microns below the surface 14.

Each tab 32 extends into a lightly doped P ⁻ substrate region 34 having a lower surface 10 to form a normally reverse biased isolation PN junction 36. The P ⁻ region 34 is approximately 1 × 10
^It has a relatively uniform net dopant concentration of ¹⁵ atoms / cm ³ . This concentration is the same as the N-type dopant concentration at the bottom of the buried region 32 along the isolation junction 36.

Isolation junction 36 is the base-collector junction of a parasitic PNP transistor that can be turned on during programming. Since each buried region 32 is completely adjacent to the oxide region 16 around its associated cell 12, N
^{The +} tab 32 forms the base portion of the parasitic PNP transistor. This reduces the current gain of those transistors from about 10 without tab 32 to about 0.1. When one of the cells 12 is programmed, the reduced amplification reduces the voltage that can form in the substrate region 34, thereby preventing the programmable diodes of other cells 12 in the same column from degrading.

Each buried region 32 includes a lower N ⁺ region 40 and an upper N ⁺ region 4
It is connected to the upper surface 14 by a corresponding composite N ⁺ region 38 of 2. The combination of N ⁺ regions 32 and 38 constitutes the necessary intermediate connection between the lower cell region 20 and the row line. The high dopant in each buried region 32 is
It serves to reduce series resistance between the connection region 38 and the lower cell region 20. Connection region 38 also forms a low resistance path to surface 14 to mitigate parasitic voltage drops that occur during programming of the cell.

The other part of the composite buried layer is a buried P ⁺ web 44 laterally surrounding each of the buried N ⁺ regions 32.
The buried web 44 adjoins the oxide region 16 along the lower surface of the oxide region 16 and extends upward along a portion of its sidewall. The average net dopant concentration in the P ⁺ web 44 is about 7 × 10 ¹⁷ atoms / cm ³ . The buried web 44 has a thickness of about 1 at the portion contacting the lower surface of the oxide region 16.
It has a net dopant concentration of × 10 ¹⁷ atoms / cm ³ . On the other hand, the P-type dopant concentration changes to the dopant concentration in the substrate region 34 at a position about 3.5 microns below the surface 14.

The P ⁺ web 44 is connected to the upper surface 14 by a plurality of low resistance P ⁺ regions 46 extending along columns in the PROM. The insulating region 16 and the buried web 44 are connected to the connecting region 46.
In combination with each other, cells 12 of individual tabs 32 are laterally electrically isolated from cells 12 of all other tabs 32.
Therefore, this combination laterally separates the rows from each other. The web 44 associated with the connection area 46 also
The collector region 34 of the PNP parasitic transistor provides a low resistance path for removing holes collected during programming of the cell. This also allows one programming of cell 12 to be transferred to another cell 12 along the same column.
Prevents damage to the programmable diode inside.

A corresponding lightly doped region comprising P ^- substrate region 34, and region 3
4 and the corresponding epitaxial N region 48 existing between the lower surface of the oxide region 16 and each of the buried regions 32,
Separated laterally from the embedded web 44. N region 48 is
Each has a relatively uniform net dopant concentration of about 8 × 10 ¹⁵ atoms / cm ³ . P ^- region 34 and N-region 4
The low doping combination with 8 ensures that the substrate isolation junction 36 has a sufficiently high breakdown voltage (typically about 30 volts).

The array of conductors in contact with a number of single crystal regions extending to upper surface 14 completes the PROM. A platinum-nickel silicide layer 50 is provided on each P ⁺ region 46, and a titanium-tungsten layer 52 is provided on the silicide. A pattern of leads 54 of aluminum with about 1% silicon is provided on N ⁺ regions 28 and 42 along surface 14 and on titanium-tungsten region 52. The lead wires 54 _B , 54 _D and 54 _F are column lines. With the exception of lead 54 _C and its counterpart connected to the row line, all other leads 54 _D are second b
Extends along a row as shown by lead 54 _{D in the} figure.

A second crossing of leads of conventional construction is used to form the row lines and complete the array of conductors. This second of the lead wire
Crossing patterns are not shown in the figure to avoid complexity. If a second pattern of leads is used, a layer of phosphorus-doped silicon dioxide (Vapox) is provided over the leads 54 and the portion of oxide region 16 between the leads 54. Cross pattern of the lead wire is made of pure aluminum overlying Vapox layer, is connected to a lead wire 54 _C and the corresponding portions thereof by the aluminum fill passageway extending through the Vapox layer.

To program the PROM, a reverse current of about 40 mA is passed through each PN junction 30 to be destroyed. For example, in the case of breaking junction 30 _D , a suitable reverse voltage is applied between leads 54 _C and 54 _D for a suitable time, typically less than 1 microsecond, to provide programmable programming. It causes avalanche breakdown in the diode, causing a specific reverse current. The programmable diode is heated until an aluminum-silicon eutectic temperature of about 577 ° C is reached. At this point, the aluminum from lead 54 _D moves through N ⁺ region 28 _D and makes an ohmic contact with P region 22 _D , thus shorting the programmable diode. Thus, based on the arrangement used, to introduce a logic "0" or a logic "1" in cell 12 _D. On the other hand, cell 12, with the programmable diode held unchanged, is in the opposite logic state.

3a to 3n show the manufacturing process of the PROM shown in FIGS. 1, 2a and 2b. In the manufacturing process, P
Boron is used as a P-type impurity for forming multiple regions of conductivity type. Unless otherwise stated, boron in the B ⁺ form is implanted. Phosphorus, arsenic and antimony are selectively used as complementary N-type dopants. Unless otherwise stated, these are ion-implanted in the form of P ⁺ , As ⁺ , and Sb ⁺ , respectively. Other suitable impurities may be used in place of these dopants. Impurities can also be introduced into the wafer by diffusion in many ion implantation processes.

Conventional cleaning and photoresist masking techniques are used to create the various insulating P and N regions. For ease of discussion, cleaning steps, steps involved in forming the photoresist mask, and other such well known steps in semiconductor technology are described.
It will be omitted from the following description. Unless otherwise stated, each etch of silicon dioxide is performed with a buffer etch consisting of about 7 parts 40% ammonium fluoride and about 1 part 49% hydrofluoric acid.

The first step of the process is N ⁺ region 32 and P ⁺ web 4
Locating for a composite buried layer consisting of 4 and. In Figure 3a, the starting material is 7-21 Ω.
A semiconductor wafer having a P ^- single crystal silicon substrate 60 having a resistivity of -cm and a thickness of about 500 microns. This wafer is placed in an oxidizing atmosphere of oxygen and hydrogen at 1000 times.
At 360 ° C. for 360 minutes, a layer 62 of silicon dioxide having a thickness of about 1.2 microns is grown along the upper surface of the substrate 60. Photoresist mask 6 having an opening above the expected location in region 32 and web 44
4 is formed on the oxide layer 62. The exposed portion of oxide layer 62 is etched for 18 minutes, leaving 800-1400 Å thick silicon dioxide in the open areas of mask 64.

After removing the mask 64, a non-critical photoresist mask 66 having a nominal thickness of 7000 angstroms and having an opening above the intended location on the tab 32 is provided on the wafer as shown in FIG. 3b. Form on top surface.
The remaining exposed portion of the oxide layer 62 is etched for 3 minutes and removed to reach the silicon substrate 60. With the mask 66 in place, antimony is implanted at a dose of 2 × 10 ¹⁵ ions / cm ² and energy of 50 kiloelectron volts (KeV) through the open region in the rest of the oxide layer 62, ^{A +} region 68 is formed.

After removing the mask 66, the silicon dioxide having a thickness of about 2000 angstroms by placing the wafer in 1000 ° C. nitrogen for 20 minutes, 1000 ° C. oxygen and hydrogen for 13 minutes, 1200 ° C. nitrogen for 75 minutes. Locating subsidence 70 is formed in the exposed area of substrate 60 by growing a layer 72 of. The high temperature during this process also causes antimony in region 68 to move further down (and laterally) into substrate 60. A non-critical photoresist mask 74 is formed on the top surface of the wafer, with a nominal thickness of 1.2 microns and a web-like opening on the buried web 44 at a predetermined location. The exposed portion of the remaining portion of the oxide layer 62 is removed by etching for 3.5 minutes until it reaches the silicon substrate 60. 2 × 10 ¹⁴ ions / cm ² with the mask 74 placed in the correct position
Of boron and energy of 180 KeV to implant substrate 60 to form P ⁺ region 76.

After removing the mask 74, the wafer is etched for 20 minutes to remove the oxide layer 72 and the rest of the oxide layer 62, as shown in Figure 3d. An arsenic-doped epitaxial layer 78 having a resistivity of about 0.7 Ω-cm 2 is grown on the exposed upper silicon surface to a thickness of about 1.75 microns by the well-known silane process. This fills regions 68 and 76 within the substrate.

Next, the oxide region 16 is formed. First of all, about 30
A layer 80 of silicon dioxide having a thickness of 0 Å is grown along the upper surface of epitaxial layer 78. This is accomplished by placing the wafer in dry oxygen at 1000 ° C. for 11 minutes. A layer 82 of silicon nitride having a thickness of about 1200 angstroms is formed according to a conventional low pressure chemical vapor deposition process.
Deposit on oxide layer 80. Next, the wafer 10
A thin layer 84 of silicon dioxide along the upper surface of the nitride layer 82 was placed in oxygen and hydrogen at 00 ° C. for 120 minutes.
To form. As shown in FIG. 3d, each positioning depression 70 is reflected in layers 78, 80, 82, 84. A photoresist mask 86 having a web-like opening corresponding to the expected position of the insulating layer 16 is formed on the oxide layer 84. The exposed portion of the oxide layer 84 is removed by etching for 1.5 minutes.

After removing the mask 86, the exposed portion of the nitride layer 82 is removed to the oxide layer 80 by etching with hot phosphoric acid at 165 ° C. for 50 minutes, as shown in FIG. 3e. Next, the exposed portion of the oxide layer 80 is removed to reach the epitaxial layer 78 by etching for 1 minute. About 6500 exposed portions of the epitaxial layer 78
Etch below Angstrom to form trench 87. This etching is performed with 250 parts of 70% nitric acid and 40 parts.
1000 parts saturated with 49 parts hydrofluoric acid and iodine
It is carried out at 23 ° C. for 5 minutes by using an etchant consisting of 1 part acetic acid.

By placing the wafer in oxygen and hydrogen at 1000 ° C. for 360 minutes, an insulating layer 16 having a depth of about 1.25 microns is formed along trench 87 as shown in FIG. 3f. Since the oxide region 16 does not extend into the substrate 60, the portion 48 of the N epitaxial layer 78 is directly below the lower surface of the oxide region 16. During this elevated temperature process, the boron in region 76 diffuses down in substrate 60 and up in epitaxial layer 78 to form P ⁺ web 44 extending to the sidewalls of region 16. Similarly, area 6
The antimony in 8 diffuses slightly downward in the substrate 60 and slightly upward in the epitaxial layer 78 to form the N ⁺ buried region 3
Form 2. In particular, the portion of the underside of the oxide region 16 on the tab 32 is due to the positioning sink 70.
About 1000 angstroms lower than the rest of the underside. The buried region 32 extends upward enough to contact at least the lowermost surface portion of the region 16.

Epitaxial layer 7 laterally adjacent to oxide region 16
The remaining N-shaped portion of 8 is used for cell 12 and connection regions 38 and 46. Each of these N-type single crystal portions intended for cell 12 has a lateral dimension below bird's beak 18 of approximately 2 microns by 2 microns.

The remaining portion of oxide layer 84 (which grows slightly during the previous high temperature step) is removed by etching for 1.5 minutes, as shown in Figure 3g. Similarly, the nitride layer 82
The remaining part of is removed by etching with hot phosphoric acid at 165 ° C. for 35 minutes. The remaining portion of oxide layer 80 is also removed by a 1 minute etch. An electrically insulating layer 88 of silicon dioxide having a thickness of about 1000 Å is grown along the exposed portion of epitaxial layer 78 by placing the wafer in oxygen and hydrogen at 900 ° C. for 26 minutes. Since this oxidation is performed at a relatively low temperature, there is no significant redistribution of impurities in tub 32 and web 44. As a result, the formation of the embedded region 32 and the embedded web 44 is almost completed.

Next, the connection regions 38 and 46 and the transistors of the peripheral circuits are arranged. A non-critical photoresist mask 90 having a nominal thickness of about 8000 angstroms and an upper opening at the connection region 38 is formed on top of the wafer. The exposed portion of oxide layer 88 is removed by a 2 minute etch. With the mask 90 in place, the epitaxial layer 78 is exposed at a dose of 3 × 10 ¹⁵ ions / cm ² and an energy of 180 KeV.
Phosphorus is implanted into the exposed portion of the N ⁺ region to form an N ⁺ region 92.

After removing the mask 90, the wafer is annealed in nitrogen at 1000 ° C. for 120 minutes to repair the lattice defects. The wafer is then placed in oxygen and hydrogen at 900 ° C. for 31 minutes to grow a layer 94 of silicon dioxide having a thickness of about 1400 Å on the exposed portion of epitaxial layer 78 as shown in FIG. 3h. During this oxidation step, the thickness of oxide layer 88 increases by approximately 1000 Angstroms. Phosphorus in region 92 redistributes and moves them downwards, and boron in web 44 diffuses slightly upwards. No significant redistribution of antimony within the tub 32 occurs during these processes.

A photoresist mask 96 is formed on top of the wafer with a nominal thickness of 1.2 microns and an opening above the P ⁺ connection region 46 at the expected location. The mask 96 is
It is non-critical for region 46. With the mask 96 in place, boron is implanted twice through the exposed portion of the oxide layer 88 and into the underlying portion of the epitaxial layer 78 to form the P ⁺ region 98. The first injection is 1x
10 ¹³ ions / cm ² dose and performed at an energy of 180 KeV, the second injection, 1.5 × 10 ¹⁴ ions /
The dose is cm ² and the energy is 75 KeV. The two boron implants also form the desired impurity distribution for the base of the NPN transistor and the emitter and collector of the PNP transistor in the peripheral circuit.

After removing the mask 96, a photoresist mask 100 having a nominal thickness of 8000 angstroms and an upper opening at the intended location in the connection region 38 is formed on the top of the wafer as shown in FIG. 3i. Mask 100
Are non-critical to region 38. Oxide layer 94
Are removed by etching for 4 minutes. First 1x
Arsenic was deeply implanted at a dose of 10 ¹⁵ ions / cm ² and an energy of 180 KeV, the mask 100 was removed, and 2
By implanting arsenic shallowly at a dose of × 10 ¹⁵ ions / cm ² and energy of 50 KeV, N ⁺ region 4
2 is formed in the upper portion of region 92. The two arsenic implants also form the desired impurity distribution for the emitter of the NPN transistor in the peripheral circuit.

The wafer is annealed in nitrogen at 1000 ° C. for 60 minutes to repair implanted lattice defects and redistribute arsenic and boron in regions 42 and 98. As shown in FIG. 3j, the region 42 extends downward. The boron in the buried web 44 spreads slightly outwardly and the region 98 extends downwardly into contact with the web 44, forming the P ⁺ connection region 46. Regions 32 and 92 also grow slightly.

Next, a diode is formed in the cell 12. A non-critical photoresist mask 102 having a nominal thickness of 1.2 microns and an opening on the cell 12 at a predetermined location is formed on top of the wafer. The exposed portion of the oxide layer 88 is
The epitaxial layer 78 is removed by etching for 5 minutes. With the mask 102 in place, boron is implanted into the epitaxial layer 78 at a dose of 3.5 × 10 ¹³ ions / cm ² and an energy of 110 KeV to form the PN junction 26. Then, similarly, arsenic was added at a dose of 6 × 10 ¹⁴ ions / cm ² and 5
It is injected into the epitaxial layer 78 with an energy of 0 KeV to form the PN junction 30. In each of these implants, the sidewalls of the insulating region 16 laterally spread the boron and arsenic impurities, and thus the junctions 26 and 30.
It functions as a mask that controls the lateral spread of the. These two implants form P region 22 and N ⁺ region 28.

After removing the mask 102, the lattice defects caused by the implantation are repaired by forming anneals in nitrogen at 950 ° C. for 5 minutes, in oxygen for 25 minutes and again in nitrogen for 5 minutes to form regions 22 and 28. To do. This anneal extends regions 22 and 28 slightly downward to their final position, as shown in FIG. 3k, thereby leaving region 20 as the remainder of epitaxial layer 78 within cell 12. Regions 42 and 92 also extend slightly downward to their final position, which is N ⁺ region 40 where region 92 contacts the associated buried region 32. Similarly, the regions 46 extend slightly downward to their final position. A layer 10 of silicon dioxide having a thickness of about 400 angstroms during the annealing process.
4 grow on the exposed silicon in regions 28 and 42 along the top of the wafer. This annealing process is
The fabrication of the diodes in the M cell and the connection regions 38 and 46 is completed.

FIG. 4 shows the final dopant concentration for either cell 12
Upper center surface 14 (underside oxide layer 104)
To tab 32 as a function of downward depth. Fourth
The view is taken, for example, along the plane 2b-2b in FIG. 2a or along a similar plane in FIG. 3k. The star reference in FIG. 4 is related to the dopant concentration and junction location of the PROM element identified by the starless reference. As shown in FIG. 4, the maximum boron concentration in each P region 22 occurs approximately midway between its PN junctions 26 and 30 in their final position.

The wafer is then placed in the regions 28,4 along the top of the wafer.
It is in the state of manufacturing the conductive lead wire which contacts 2,46. A non-critical photoresist mask 106 having an opening over P ⁺ region 46 is formed along the top of the wafer. The oxide regions 88 are removed by etching for 4 minutes to reach regions 46.

After removing the mask 106, approximately 250 Å of platinum containing 60% nickel is deposited on the top surface of the wafer by conventional sputtering techniques. The wafer is then sintered at 475 ° C. and deposited with 3 liters of platinum / nickel deposited on the exposed silicon in connection area 46.
Convert to a layer 50 of platinum-nickel silicide as shown. The platinum / nickel not converted to silicide is removed by etching with aqua regia. About 100
A layer of titanium-tungsten having a thickness of 0 Å is deposited on top of the wafer. Next, a layer of aluminum is deposited to a thickness of about 1000 angstroms on the top of the wafer, including on titanium-tungsten. A photoresist mask 108 is formed on top of the wafer in which polymerized photoresist generally overlies region 46. The exposed aluminum is etched away with a conventional aluminum etch, leaving the aluminum regions 110 and the resulting exposed titanium-tungsten etched with hydrogen peroxide, leaving the titanium-tungsten layer 52.

After removing the mask 108, a third non-critical photoresist mask 112 having a polymerized photoresist overlying the composite sandwich structure of the regions 50, 52, 110 is provided.
It is formed on the top surface of the wafer as shown in FIG. Oxide layer 104 with 20 parts of 40% ammonium fluoride and 1
Parts by etching with a buffer etchant consisting of 49% hydrofluoric acid for 1.7 minutes to expose N ⁺ regions 28 and 42.

After removing the mask 112, the aluminum layer 110 is removed by etching. A layer of aluminum containing 1% silicon is deposited on top of a 7000 Å thick wafer. The exposed aluminum is formed by forming a photoresist mask 114 on the aluminum layer so that the polymerized photoresist overlies regions 28 and 42 and then etching with a standard aluminum etchant as shown in FIG. 3n. And the aluminum layer is patterned to form leads 54. The mask 114 is then removed to form the structure shown in Figure 2a (and Figure 2b).

As noted previously, the second layer of aluminum lead is provided in the conventional manner. This is accomplished as follows. That is, a layer of Vapox is deposited on the top of the wafer to a thickness of about 9000 angstroms, and a suitable photoresist mask is used to etch the vias to either selected lead 54 and Vapox. A layer of pure aluminum is deposited on top and on selected leads 54, and another layer of photoresist is used to pattern this layer of aluminum to complete the PROM. Although the present invention has been described with reference to particular embodiments, it is understood that the invention is not limited to the embodiments. For example, the connection area for the composite buried layer can be located after the placement of the diode in the PROM cell. Alternatively, the connection area for the composite buried layer and the diode for the PROM cell can be placed by using a similar implantation / diffusion process. Materials and dopants of opposite conductivity type can be used in place of the materials and dopants described above. Therefore, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the scope and spirit of the present invention.

[Brief description of drawings]

FIG. 1 is a sectional arrangement view of one embodiment of the PROM of the present invention, and FIGS. 2a and 2b are 2a-2 of FIG. 1, respectively.
A sectional view taken along the line a, sectional views taken along the line 2b-2b, and FIGS. 3a to 3n are sectional views showing respective steps of the manufacturing process of the embodiment shown in FIG. 1, and correspond to the sectional view shown in FIG. 2a. FIG. 4 and FIG. 4 are graphs showing the graph of the dopant concentration of a typical PROM cell of the present invention. 12 ... Cell 16 ... Electrical insulation region 20 ... Lower N region 22 ... Intermediate P region 26 ... First PN junction 28 ... Upper N ⁺ region 30 ... Second PN junction 32 ... Buried region 36 ... ... Separation PN junction 38 ... Composite N ⁺ region 40 ...... Lower N ⁺ region 42 ...... Upper N ⁺ region 44 ...... P ⁺ web 50 ...... Platinum-nickel silicide 52 ...... Titanium-tungsten layer 54 ...... Lead wire 60 ... P single crystal silicon wafer 62, 72, 80 ... Silicon dioxide layer 66, 86, 96 ... Photoresist mask 70 ... Positioning depression 78 ... Epitaxial layer 82 ... Silicon nitride 110 ... Aluminum area

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ronald Lee Klein 95030 Los Gates Aurora Lane 107 (56) Reference JP-A-57-194566 (JP) , A) JP-A-53-119690 (JP, A) JP-A-53-24786 (JP, A)

Claims (7)

[Claims] 1. A programmable cell comprising a semiconductor body having an electrically insulating region and a semiconductor region, the semiconductor region being formed in a surface region of the semiconductor region and laterally separated from each other by said electrically insulating region. A programmable semiconductor device having a group, each programmable cell being laterally surrounded by said electrically insulating region,
Each programmable cell has a first PN junction formed by a lower region of the first conductivity type and an intermediate region of the second conductivity type,
A second PN junction formed by the intermediate region and an upper region of the first conductivity type, the first and second PN junctions forming a pair of PN junction diodes connected in anti-series with each other; In the programmable semiconductor device in which the PN junction is adjacent to the electrically insulating region at all of these edges, the semiconductor region is a plurality of buried regions of the first conductivity type that are separated from each other, and The buried region having an average net dopant concentration that is higher than the average net dopant concentration of the lower region and is adjacent to at least one underside of the lower region; A second conductivity type buried web having a high conductivity and laterally surrounding each buried region, and a space extending between the buried web and the surface of the semiconductor region and located between at least two programmable cells. At least one connection region of the second conductivity type to be placed, and having at least an average net dopant concentration lower than the buried region and the buried web, at least along the lower surface of the buried region and the buried web. A programmable semiconductor device comprising: a buried region and a buried web adjacent to the buried web. 2. The programmable semiconductor device according to claim 1, wherein the cells are arranged in an array of rows and columns in a lateral direction, and at least one connection region comprises:
Programmable, contacting one conductor of a set of conductors extending substantially parallel to each other on the surface of the semiconductor region, each conductor being located between a pair of different columns. Semiconductor device. 3. A programmable semiconductor device according to claim 1 or 2, wherein the lightly doped region is insulated upward along the buried region and the entire lateral edge of the buried web. A programmable semiconductor device that extends to a region and separates a buried web from the buried region. 4. A programmable semiconductor device as claimed in any one of claims 1 to 3, wherein the average net dopant concentration in the buried web and the buried region is the average net dopant concentration in the lightly doped region. A programmable semiconductor device characterized in that it is at least an order of magnitude higher than the dopant concentration. 5. A programmable semiconductor device according to claim 1, wherein a set of second conductivity types extending from the buried web to the surface of the semiconductor region and laterally separated from each other. Connection regions are provided, which reach the surface of said semiconductor region in a very evenly distributed region over the part of the surface of said semiconductor region in which the cells are located, A programmable semiconductor device, wherein each of the conductors is in contact with one of a set of conductors extending substantially parallel to each other on the surface of the semiconductor region. 6. A programmable semiconductor device according to claim 1, wherein the maximum net dopant concentration of the intermediate region for each cell is from the midpoint between its two PN junctions to between these PN junctions. A programmable semiconductor device characterized in that it occurs at a vertical distance of 20% or less of the distance. 7. The programmable semiconductor device according to claim 6, wherein the first PN junction is formed by an interface between the intermediate region and the lower region of the first conductivity type, and each first PN junction is an array. A programmable semiconductor device, which is an element, wherein each second PN junction is a programmable element.