JPH0644609B2 - Junction break type PROM - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a programmable read-only junction breakdown PROM.

[Conventional technology]

Programmable read-only PROM (Programabl
The e Read Omly Memory) is required to have a particularly reliable program (writing) in view of its use. This PRO
The reliable program of M is to surely select the storage element to be stored and to stably supply the current.

Conventionally, when a PROM of this type is configured by a bipolar element, an element including two PN junctions connected in opposite directions is usually used as a unit memory element, and one of the two PN junctions is used. A junction breakdown PROM that is destroyed to write information is used, and a fuse and a device including one PN junction connected to the fuse are used as a unit storage element, and the fuse is blown to write information. The fuse-type PROM to be used has been put into practical use.

Conventionally, in the circuit configuration of this type of junction breakdown type PROM, as shown in FIG. 4, the storage elements Q ₁₁ to Wn are connected to the intersections of the word lines W ₁ , W ₂ ... Wn and the bit lines B ₁ , B ₂ ... Bm. Qmn
Is provided, and the word driver WD is provided at the end of the word line.
₁ , WD ₂ ... WDn are connected.

Now, the case where information is written into the storage element Q ₁₁ selects the bit lines B ₁ and the word line W _1, and is absorbed from the bit line B ₁ word driver WD ₁ pouring write current.

FIG. 5 is a plan view showing the main part of FIG. 4, in which a plurality of strip-shaped collector regions 4 are provided on the semiconductor substrate 1 and the insulating region 3 is provided between the strip-shaped collector regions 4. Each strip-shaped collector region 4 is independent. In the strip-shaped collector region 4, a plurality of base regions 6 and emitter regions 7 are provided in a row to form storage elements Q _{11 to} Qnm. Within the strip-shaped collector region 4, collector electrodes 8 are further provided for every 2 to 8 storage elements, and word lines W ₁ and W
₂ ... Connected to Wn. In addition, the memory elements Q _{11 to} Q
The emitter region 7 of mn is connected via the emitter electrode 7 ',
It is connected to the bit lines B ₁ , B ₂ ... Bm.

FIG. 6 is a cross-sectional view showing a main part of one row of a conventional PROM. Reference numeral 1 is a semiconductor substrate, 2 and 4 are connected to a word line, a collector buried layer and a collector region, 3 and 3'are insulating regions connected from a substrate electrode 9 for extracting a potential of the semiconductor substrate to a ground line 11, and 5 are selected. An oxide region, 6 is a base region, and 7 is an emitter region connected to the bit line 10.

[Problems to be solved by the invention]

In such a conventional pattern configuration, as shown in the plan view of the chip of FIG. 7, the ground line B is arranged around the matrix area A of the storage element, so that the unit storage element The distance to the ground line 11 is very long, and a part of the write current that flows from the bit line 10 passes through the semiconductor substrate 1 and is absorbed by the ground line 11 before the potential with respect to the ground line 11. Rises, the parasitic thyristor (parasitic pnpn effect) operates, and the write current is dispersed. Therefore, a sufficient write current does not flow to the memory element,
Writing failure occurs.

Next, this mechanism will be briefly described with reference to FIGS. 8 (a) and 8 (b). The bit line B ₁ and the word line W ₂ are selected to write information in the storage element Q ₂ . At this time, for example, if there is a written storage element Q ₁ in the adjacent word line W ₁ , as shown in the equivalent circuit of FIG. 5B, the bit line B ₁
Between the word line _{W 2} and the storage element _{Q 2} (Emitter
And a diode D consisting of base junction is divided base, a collector, a pnp transistor Q _'2 consisting of the substrate (P-type). ) And a pnp transistor Q ′ ₁ composed of a base, a collector and a substrate of the memory element Q ₁ , and a pnp transistor Q ′ ₁ composed of a collector of the memory element Q ₂ , a substrate and a collector of the memory element Q _1.
Connected in parallel via a transistor Q _T ,
It becomes the same structure as the parasitic thyristor of pnpn structure was connected.

The write current I from the bit line _{B 1} to the storage element _{Q 2} is poured, when it is absorbed to the word driver WD _{2, 'the} collector current I.alpha ₂ (alpha ₂ of ₂ transistors _Q' transistor Q in the current amplification factor of ₂ Flow through the insulating region or the semiconductor substrate toward the ground line G. If the equivalent resistance from the storage element Q ₂ to the ground line G at this time is R, the potential at the point S is I with respect to the ground line G.
Increase to α ₂ R.

On the other hand, when the potential of the word driver WD ₂ during operation is V, the potential at the point P rises to V with respect to the ground line,
The potential difference between the S point and the P point is Iα ₂ R−V,
When the write current I increases until (Iα ₂ R−V)> (forward voltage VF between the emitter and base of the transistor Q _T ), the transistors Q ′ ₁ and Q _{T start} to draw current and the parasitic thyristor operates. Then, the write current I is dispersed. Therefore, a sufficient write current does not flow to the storage element and a write failure occurs.

For example, the write current I = 100 mA, the transistor Q _'2 in the current gain alpha ₂ = 0.05, the equivalent resistance R = 500 [Omega from the storage element to a ground line, and 0.5V potential during operation of the word driver WD, the transistor _{Q T} the _{V F}
Assuming 0.8 V, the potential difference between the S point and the P point becomes Iα ₂ R
-V = 2V next transistor becomes greater than _{V F} 0.8 V of _{Q T,} a parasitic thyristor is easily operated.

Therefore, an object of the present invention is to provide a junction breakdown type PROM which has a simple structure and enables reliable programming by eliminating a parasitic thyristor working between storage elements.

[Means for solving problems]

The junction breakdown type PROM of the present invention has a plurality of collector regions provided on a semiconductor substrate of one conductivity type and arranged in an island shape and arranged in a matrix, and is connected to a lower portion of the collector region and is provided in the semiconductor substrate. A buried buried layer of a high impurity concentration of the reverse conductivity type, an element insulating region of a high conductivity of a single conductivity type that is buried in the semiconductor substrate between the collector regions to separate the collector regions, and the collectors. At least one collector electrode in the region, a plurality of one-conductivity-type base regions arranged in a row on both sides of the collector electrode in the collector region, and reverse electrodes provided in each of the base regions. The device is provided between a conductive type emitter region, an emitter electrode connected to the emitter region, and collector regions adjacent to each other on the extension of the arrangement of the collector electrode and the emitter electrode. A substrate electrode for extracting a substrate potential connected to the edge region, a word line connected to the collector electrode and arranged in parallel with the array of the collector electrode and the emitter electrode, and a word line connected to the emitter electrode and orthogonal to the word line And a ground line connected to the substrate electrode and arranged in parallel with the bit line.

[Action]

As described above, according to the present invention, the collector electrode in the collector region, the emitter electrode in the emitter region and the substrate electrode in the insulating region are arranged in a line, and the ground line connecting to the substrate electrode is connected to the emitter electrode. It is configured to be parallel to the lines, and is characterized in that there is a substrate electrode connected to the ground line in the vicinity of the memory element, and therefore has an effect of eliminating a parasitic thyristor that acts between the memory elements.

That is, according to the present invention, since the distance from the storage element to the ground line is short, the equivalent resistance of the insulating region from the storage element to the ground line and the semiconductor substrate is small, and a part of the write current flows to the insulating region and the semiconductor substrate. Even if the leakage occurs and is absorbed by the ground line, the rise in the potential with respect to the ground line is small and the parasitic thyristor does not operate. Therefore, most of the write current can be supplied to the selected storage element, and stable (and reliable) programming (writing) can be performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an essential part of an embodiment of a junction destruction type PROM of the present invention, and FIG. 2 is a partial sectional view thereof.

In the present embodiment, a plurality of N-type collector regions 4 are provided on the P-type semiconductor substrate 1 so as to be separated into islands and arranged in a matrix, and between the semiconductor substrate 1 and the collector regions 4. A buried N-type high-impurity-concentration collector buried layer 2, a high-impurity-concentration P-type insulating region 3 buried in the semiconductor substrate 1 between the collector regions 4, and a line in the collector region 4. Four P-type base regions 6 provided and N-type emitter regions 7 provided in the base regions 6, respectively.
Substrate electrodes 9 provided between the collector regions 4 adjacent to each other on the extension of the arrangement of the collector electrodes 8 and the emitter electrodes 7'in the collector region 4 and connected to the element insulating region 3 are arranged in a line. Bit line B _{1 which is provided} and whose emitter electrode 7'is orthogonal to the array of collector electrode 8 and emitter electrode 7 '
Connected to .about.B _6, the collector electrode 8 is connected to the word line _W 1, _{W 2} perpendicular to the bit lines, ground lines _G 1 arranged in parallel to the substrate electrode 9 bit lines _B 1 ~B _{6, G 2} Connected to.

Thus, this embodiment, in the vicinity of the memory element Q ₁₁ to Q _62, because of the ground wire from the storage element, therefore the distance to the ground line is short, equivalent from the storage element to a ground line low anti Even if part of the write current leaks to the insulating region 3 and the semiconductor substrate 1 because R is small, the rise in the potential with respect to the ground line is small and the parasitic thyristor does not operate.

For example, from the equivalent circuit of FIG. 8 (b), write current I =
Current amplification factor of 100 mA transistor Q ′ ₂ α ₂ = 0.0
5, 50 [Omega the equivalent resistance R ', 0.5V potential V during operation of the word driver WD, the _{V F} of the transistor _{Q T} 0.8
Assuming V, the potential difference between the S point and the P point is Iα ₂ R′-V =
It becomes −0.25V, which is lower than the V _{F of the} transistor Q _T , and the parasitic thyristor does not operate. As described above, in this embodiment, since the parasitic thyristor does not operate, most of the write current can be passed to the selected storage element, and stable and reliable programming (writing) can be made possible.

In this embodiment, a storage element is placed between the substrate electrodes 9 and 9 '.
However, in the present invention, the distance at which the parasitic thyristor does not operate can be selected according to the size of the equivalent resistance from the storage element to the ground line, and the number of storage elements between the substrate electrodes 9 can be freely selected. . FIG. 3 shows an embodiment in which eight storage elements are provided between each substrate electrode 9.

Therefore, in the present invention, at least one or more storage elements can be provided between the substrate electrodes.

Further, in the above embodiment, for convenience of explanation, the bit line,
Although the number of word lines, storage elements and ground lines is limited,
Obviously, the invention is not limited to these.

Further, in the above description, the P-type semiconductor substrate is used, but the same applies when an N-type semiconductor substrate is used.

〔The invention's effect〕

As described above in detail, the junction breakage type PRO of the present invention
In M, the collector electrode in the collector region, the emitter electrode in the emitter region and the substrate electrode in the insulating region are arranged in a line, and the ground line connected to the substrate electrode is parallel to the bit line connected to the emitter electrode. The number of storage elements between the substrate electrodes can be selected from the equivalent resistance from the storage element to the ground line at a distance that the parasitic thyristor does not operate, and at least one storage element can be provided. . Therefore, the parasitic thyristor does not operate, and most of the write current can be made to flow to the selected memory element, and the effect that stable and reliable programming can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing an essential part of an embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3 is a plan view showing an essential part of another embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram showing an example of a conventional junction breakdown type PROM, FIG.
FIG. 7 is a partial sectional view thereof, FIG. 7 is an explanatory view of a chip plane thereof, and FIGS. 8A and 8B are explanatory views of a parasitic thyristor in a junction breakdown type PROM. 1 ... Semiconductor substrate, 2 ... Collector buried layer, 3 ... Insulation region, 4 ... Collector region, 5 ... Selective oxidation region, 6
... base region, 7 ... emitter region, 7 '... emitter electrode, 8 ... collector electrode, 9 ... substrate electrode, 10 ...
... bit line, 11 ...... ground _{lines, B 1, B 2, ...} , Bm ...
... bit _{line, G 1,} G _2, ...... ground _line, Q 11 _~Qmn
...... memory _{element, WD 1, WD 2, ...} , WDn ...... word driver.

Claims (1)

[Claims] 1. A plurality of opposite-conductivity-type collector regions, which are separated from each other and arranged in a matrix on a one-conductivity-type semiconductor substrate, and a one-conductivity-type isolation buried in the semiconductor substrate between the collector regions. A region, at least one collector electrode provided in the collector region, a plurality of one-conductivity-type base regions arranged in a row on both sides of the collector electrode in the collector region, and on the base region A substrate provided between the emitter electrode connected to the opposite conductivity type emitter region and the collector region adjacent to each other on the extension of the arrangement of the collector and the emitter electrode and connected to the insulating region. An electrode, a word line connected to the collector electrode and disposed between the collector regions parallel to the array of the collector and emitter electrodes and adjacent to each other, and the word line. Perpendicular bit lines in the word line is connected to the electrode, the junction breakdown type PROM which is characterized in that a connecting line parallel with the bit line connected to the substrate electrode.