JPS61150367A - Junction breakdown type prom - Google Patents

Abstract

PURPOSE:To remove a parasitic SCR by aligning a collector electrode in a collector layer, an emitter electrode in an emitter layer and a substrate electrode in an insulating region and making a grounding line connected to the substrate electrode parallel with a bit line connected to the emitter electrode. CONSTITUTION:An N collector layer 4 and an N<+> layer 2 are insulated by a P<+> layer 3 on an N<+> buried layer 2 on a P-type Si substrate 1, a P base 6 is formed into the N layer 4 and an N emitter layer 7 into a base, and a collector electrode 8, an emitter electrode 7' and a substrate electrode 9 in the insulating layer 3 are aligned. The emitter electrode 7' is connected to bit lines B1-B6, the collector electrode 8 to word lines W1, W2 and the substrate electrode 9 to grounding lines G1, G2, and the grounding lines G1, G2 are fitted in parallel with the bit lines B1-B6. Since there are grounding lines in the vicinity of memory cells Q11-Q62, equivalent resistance among the cells is reduced, and potential slightly rises to the grounding lines and a parasitic SCR does not operate even when writing currents partially leak to the insulating layer 3 and the substrate 1. Accordingly, the greater part of writing currents flow through the selected memory cells, thus resulting in stable and positive programming.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a read-only, junction-destructive FROMK which is applied to a semiconductor device and is trap programmable.

[Conventional technology]

Programmable read-only FROM (Pro-g
ramable Read OmIy Memnry
), from the point of view of its intended use, a very reliable program (writing) is desired. To reliably program this FROM, it is necessary to reliably select the memory element to be stored and to stably supply a current.

Conventionally, when this type of FROM is constructed using bipolar elements, an element containing two PN junctions connected in opposite directions is usually used as a unit memory element, and one of these two PN junctions is A junction-destructive FROM is used to write information when it is destroyed, and an element that includes a heat and a PN junction connected to it is used as a unit memory element. A single-fuse type FROM has been put into practical use.

Conventionally, in the circuit configuration of this type of junction wave l-type FROM, as shown in FIG. Element Ql
1 to Q- are provided, and word drivers WD1 . WD, . . . WDn are connected.

Now, when writing memory element QltK information, bit line Bl and word line W! Select and beep) #Bt
Write current is applied from the word dry, <-WD
1 is absorbed.

FIG. 5 is a plan view showing the main part of FIG. 4, in which a plurality of strip-shaped collector regions 4 are provided on the semiconductor substrate 1, and an insulating region 3 is provided between the strip-shaped collector regions 40, and each The strip-shaped collector region 4 is made independent. Inside the strip-shaped collector region 4, a plurality of base regions 6. An emitter region 7 is provided to constitute memory elements Q11 to Q1. In the strip-shaped collector region 4, collector electrodes 8 are further provided for every 2 to 8 memory elements, and are connected to the word lines W1.about.Wn. In addition, the memory element Qt
The emitter region 7 at tQ% is connected to the bit line B1. through the emitter electrode 7'. B2...B m K connected.

FIG. 6 is a sectional view showing a main part of an example of a conventional FROM. 1 is a semiconductor substrate, 2 and 4 are a collector buried layer and a collector region connected to a word line, 3° 3' is an insulating region connected from a substrate electrode 9 for taking out the semiconductor substrate potential to a ground line 11, and 5 is a selection. The oxidized region 6 is a base region, and 7 is an emitter region connected to a bit line 10.

[Problem that the invention seeks to solve]

In such a conventional pattern configuration, as shown in FIG. 7, the distance from the unit storage element to the ground s11 is very long, and a part of the write current flowing from the bit line 1o is By the time it passes through the semiconductor substrate 1 and is absorbed by the ground 411, the potential increases with respect to the ground line 11, a parasitic thyristor (parasitic pnpn effect) operates, and the write current is dispersed. Therefore, a sufficient write current does not flow to the memory element, resulting in a write failure.

Next, this mechanism will be briefly explained with reference to FIGS. 8(a) and 8(fb). Bit line B1 and word 4W2 are selected to write memory element QzK information. At this time, for example,
Assuming that there is a written memory element Q1, the adjacent word line WtK is 1 as shown in the circuit shown in FIG. 5 fb).
Between the bit line B and the word line W2, there is a storage element Q2 (a diode D with an emitter-base junction).
and pnp (consisting of base, collector, and substrate (P type))
It is divided into run lister Q'2. ), and the pnp transistor Slith'1 consisting of the base, collector, and substrate of the storage element Q1 is connected to the storage element Q! collector, substrate, memory element Q1
are connected in parallel via a npn) run ristor QT consisting of a collector, resulting in the same structure as that of a parasitic thyristor of a so-called pnpn structure.

Bit#i! When the write current flows from B+ to the memory element Q2 and is absorbed into the word driver WD, the collector current α, (α2
is the current amplification factor of the transistor Q'2. )#'i,
It flows towards the ground line G through the insulating region or the semiconductor substrate. If the equivalent resistance from the memory element Q2 to the ground line G at this time is R, the potential at 8 points rises to ■α2R with respect to the ground and 4G.

On the other hand, if the potential during operation of word driver WD2 is V, the potential at point P rises to V with respect to ground at<
The potential difference between point 8 and point P is α2R−v toy!
7. When the write current I increases until (Iat - V) > () run risk QT emitter-pace forward voltage VF), transistors Q'l and QT start to draw current, and the parasitic thyristor As a result, the write current I is dispersed. Therefore, a sufficient write current does not flow to the memory element, resulting in a write failure.

For example, injected current I=100mA,) run risk Q
'z current amplification factor α, = Q, Q5, equivalent resistance R from the storage element to the ground line = 500 Ω, the operating potential of the word driver WD is 0.5 V, and the voltage of the transistor QT is
If F is 0.8 V, the potential difference between point 8 and point P is
α2 - V = 2V, so Vy of transistor QT
The parasitic thyristor operates easily.

Therefore, an object of the present invention is to provide a junction destruction type FROM which has a simple structure and enables reliable programming by eliminating the parasitic thyristor that acts between memory elements.

Means for Solving Problem C] The junction breakdown type FROM of the present invention is a junction breakdown type PROM having a memory element at the intersection of a plurality of word lines and bit lines.
, a plurality of collector regions of opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a highly impurity collector buried layer of opposite conductivity type buried between the semiconductor substrate and the collector region. a highly impurity-concentrated one-conductivity insulating region buried in the semiconductor substrate between the respective collector regions; a plurality of one-conductivity type base regions provided in a line within the collector regions; a collector electrode in the collector region, an emitter electrode in the emitter region, and a substrate electrode in the insulating region are provided in a line; The electrode is connected to a bit line, the collector electrode is connected to a word line, and the substrate electrode is connected to a ground line. Further, the ground @ is provided parallel to the bit line.

[Effect]

In this way, one aspect of the present invention is that the collector electrode in the collector region, the emitter electrode in the emitter region, and the substrate electrode in the insulating region are arranged in a line, and the ground line connected to the substrate electrode is connected to the emitter electrode. The feature is that there is a substrate electrode that is configured to be parallel to the line and connected to the ground line near the memory element, which has the effect of eliminating parasitic silicon risk that acts between the memory elements.

That is, according to the present invention, since the distance from the memory element to the ground line is short, the equivalent resistance of the insulating area and the semiconductor substrate from the memory element to the ground line is small, and a portion of the write current is transferred to the insulating area and the semiconductor substrate. Even if leakage occurs and is absorbed by the ground line, the potential rise with respect to the ground line is small and the parasitic thyristor does not operate. Therefore, most of the write current can be passed to the selected memory capacitor, and programming (writing) can be performed stably and reliably.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a main part of an embodiment of a joint-break type PROM of the present invention, and FIG. 2 is a partial sectional view thereof.

This embodiment includes a plurality of N-type collector regions 4 provided on a P-type semiconductor substrate 1 and an N-type collector buried with a madder impurity concentration buried between the semiconductor substrate 1 and the collector region 4. a P-type insulating region 3 with a high impurity concentration buried in the semiconductor substrate 1 between the collector regions 4, and four P-type insulating regions 3 provided in a row in the collector region 4. It includes a base region 6 and an N-type emitter region 7 provided within the base region 6, and a collector region 4.
The collector electrode 8 in the inner region, the emitter electrode 7' in the emitter region 7, and the substrate electrode 9 in the rice feeding region 3 are arranged in a line, and the emitter electrode 7'
The collector electrode 8 is connected to the words @Wt and W*, and the substrate electrode 9 is connected to the ground @Gt and GgK, respectively. Also, ground 4Gt, G2 is bit line 81~B
The trap is set parallel to 6.

That is, in this embodiment, the collector electrode 8 in the collector region 4, the emitter electrode 7' in the emitter region 7, and the substrate chamber tf! in the insulating region 3. , 9 are lined up in a row, and the ground lines GK and G2 connected to the substrate electrode 9 are parallel to the bit lines B1 to B6 connected to the emitter electrode 7'.

In this way, in this embodiment, the memory elements Q t t~Qsz
Since there is a trap and a ground line near the ground line, the distance from the memory element to the ground line is short, so the equivalent resistance R from the memory element to the ground line is small, and the insulation region 3 and semiconductor substrate IK,
Even if part of the write current leaks, the potential rise with respect to ground aK is small and the parasitic thyristor does not operate.

For example, from the equivalent circuit of FIG. 8 (bl), write voltage 15
fEI=100mA) Current amplification group α of run lister Q'z
, ==Q, Q5, equivalent resistance 几′ is 50Ω, potential V during operation of word driver WD is 0.5V, ) run lister Q
If vr of r is 0.8v, the potential difference between point 8 and point P is
Ia, R'-V=-0,25V to fxF), lower than the V of transistor QT, the parasitic thyristor does not operate. In this way, in this example, since the parasitic thyristor does not operate, most of the write current can flow to the selected memory element, resulting in stable and reliable programming (
v# import).

In this embodiment, four memory elements are arranged between substrate electrodes 9 and 9'.
However, in the present invention, the distance at which the parasitic thyristor does not operate can be selected depending on the size of the equivalent resistance from the memory element to the ground line, and the number of memory elements between each substrate electrode 9 can be freely selected. .

FIG. 3 shows an embodiment in which eight memory elements are provided between each substrate electrode 9. In FIG.

Therefore, in the present invention, at least one memory element can be provided between f'i and the substrate electrodes.

In addition, in the above embodiment, for convenience of explanation, the bit line,
Although limiting the number of word lines, storage elements and ground lines,
It is clear that the invention is not limited thereto.

Further, in the above description, a P-type semiconductor substrate is used, but the same applies when an N-type semiconductor substrate is used.

〔Effect of the invention〕

As explained above in detail, the junction breaking type FRO of the present invention
In M, the collector electrode in the collector region, the emitter electrode in the emitter region, and the substrate electrode in the disconnected region are arranged in a line, and the ground line connected to the substrate electrode is the emitter IE1.
It is configured to be parallel to the bit line connected to tLK,
The number of memory elements between the substrate electrodes can be selected from the equivalent resistance from the memory element to the ground line at a distance at which the parasitic thyristor does not operate, and at least one or more memory elements can be provided. Therefore, the parasitic thyristor does not operate,
Most of the write current can be passed to the selected memory element, resulting in the effect that programming can be performed stably and reliably.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a main part of an embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3 is a plan view showing a main part of another embodiment of the invention, and FIG. A circuit diagram showing an example of a conventional junction-broken type FROM; FIG. 5 is a plan view showing the main parts;
The figure is a partial cross-sectional view of the same, FIG. 7 is an explanatory diagram of the chip plane, and FIG. 1...Semiconductor substrate, 2...Collector buried layer, 3...Excellent region, 4...Collector region, 5...Selection Oxidation region, 6...
・Base region, 7...Emitter region, 7'...
...Emitter electrode, 8...Collector electrode,
9...Substrate electrode, 10...Bit line,
11... Ground wire, at, 82,...
Bm... Bit line, Gl, G2... Ground line s Qs1~Qmn... Memory element, WD
,,WD2. ...,WDn...Word driver O

Claims (3)

[Claims] (1) In a junction breakdown type PROM having a memory element at the intersection of a plurality of word lines and a bit line, a plurality of collector regions of opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a plurality of collector regions of the opposite conductivity type provided on a semiconductor substrate of one conductivity type, a collector buried layer with a high impurity concentration of the opposite conductivity type buried between the collector regions; an insulating region with a high impurity concentration of one conductivity type buried in the semiconductor substrate between the collector regions; A collector electrode in the collector region and a plurality of base regions of the opposite conductivity type provided in the base regions, each having a plurality of base regions of one conductivity type provided in a line in the region, and emitter regions of opposite conductivity type provided in the base regions, and a collector electrode in the collector region and a collector electrode in the emitter region. An emitter electrode and a substrate electrode for taking out a semiconductor substrate potential in the insulating region are arranged in a line, and the emitter electrode is connected to a bit line, the collector electrode is connected to a word line, and the substrate electrode is connected to a ground line. A junction-destructive PROM characterized by
. (2) The junction breakdown type PROM according to claim (1), wherein at least one memory element is provided between the substrate electrodes provided in one row. (3) A junction breakdown type PROM according to claim (1), wherein the ground line is provided parallel to the bit line.