JPS61154163A - Junction breakdown type prom - Google Patents

Abstract

PURPOSE:To ensure stable writing in memory cells (to program), by providing a substrate electorode in a memory element matrix, thereby preventing the operation of a parasitic thyristor. CONSTITUTION:A collector electrode 8 in a collector region 4, an emitter electrode 7' in an emitter region 7 and a substrate electrode 9 in an insulating region 3 are provided in a matrix region A of memory elements, in a Figure of chip pattern arrangement. A grounding line G, which is connected to the substrate electrode, is made parallel with word lines W1 and W2, which are connected to the collector electrodes 8. since the grounding line is located in the vicinity of the memory elements, the distance from each memory element to the grounding line is short. Therefore, the equivalent resistance R from the memory element to the grounding line is small. Even if part of writing current leaks into the insulating region 3 and a semiconductor substrate 1, the increase in potential with respect to the grounding line is small, and a parasitic thyristor is not operated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a programmable read-only junction destruction type PROM.

[Conventional technology]

Programmable read-only FROM (Pro-g
ramable Read 0m1y Memory)
From the viewpoint of its use, it is important to reliably select a memory element to store a particularly reliable program (write) and to stably supply a current.

Conventionally, when this type of FROM is configured with bipolar elements, an element including two PN junctions connected in opposite directions is usually used as a unit memory element, and one of the two PN junctions is A junction-destructive PROM that can be destroyed to write information, and an element containing one PN junction connected to a wire as a unit memory element are used, and this wire is fused to write information. A fuse-type FROM in which data can be written has been put into practical use.

Conventionally, in the circuit configuration of this type of junction breakdown type FROM, as shown in FIG.
A word line 24A- is provided at the end of the word line.
WDI, WD2...WDn are connected.

Now, when writing information to the storage element Qss, the bit line B1 and the rad line Wl are selected, and a write current is applied from the bit line B1 and absorbed by the word driver WD.

FIG. 5 is a plan view showing the main part of FIG. 4, in which a plurality of strip-shaped collector regions 4 are provided on the semiconductor substrate 1, and an insulating region 3 is provided between the strip-shaped collector regions 40. The strip-shaped collector regions 4 are made independent. Inside the strip-shaped collector area 4, there are a plurality of pace areas 6. in the - column. An emitter region 7 is provided to constitute memory elements Qu to Qmn. The strip-shaped collector region 4 further includes a memory element 2.
A collector electrode 8 is provided for every eight word lines W1. W2
...Connected to Wn. In addition, the memory elements Q11~
The emitter region 7 of Qmn is connected to bit lines Bl, B2 . . . Bm via emitter electrodes 7'.

FIG. 6 is a sectional view showing a main part of an example of a conventional FROM. 1 is a semiconductor substrate, 2 and 4 are a collector buried layer and a collector region connected to a word line, 3°3' is an insulating region connected from a substrate electrode 9 for taking out the semiconductor substrate potential to a ground line G, and 5 is a selection. In the oxidation range, 6 is a pace region, and 7 is an emitter region connected to a bit line 10.

[Problem that the invention seeks to solve]

In such a conventional pattern configuration, as shown in the plan view of the chip in FIG. 7, a ground IIi! Since the configuration is such that G is arranged so as to surround G, the distance from the unit memory element to the ground line G is very long, and a part of the write current flowing from the bit line IO passes through the semiconductor substrate 1. Before being absorbed by the ground line G, the potential increases with respect to the ground line G, a parasitic thyristor (parasitic pnpn effect) operates, and the write current is dispersed. Therefore, a sufficient write current does not flow to the memory element, resulting in a write failure.

Next, this mechanism will be briefly explained with reference to FIGS. 8(a) and 8(b). Bit line B1 and word line W2 are selected to write information to storage element Q2. At this time, for example,
Assuming that there is a written memory element Q1 on the adjacent word line Wl, as shown in the equivalent circuit in the third figure),
A storage element Qg is connected between the bit line B1 and the word line W2.
(Diode D consisting of an emitter-paste junction,
The pnp transistor is divided into a Q-type transistor consisting of a conductor, a collector, and a substrate (P type). ), a pnp transistor consisting of the memory element Q1's pace, collector, and substrate) transistor Q1
are connected in parallel via a PnP (PnP) transistor QT consisting of the collector of the storage element Q2, the substrate, and the collector of the storage element Q1-, resulting in the same structure as that of a so-called pnpn parasitic thyristor connected.

When a write current flows from the bit line Bl to the memory element Q2 and is absorbed into the word driver WD, the collector current α2 of the transistor Q'x (α2 is the current amplification factor of the transistor Q'z). flows through the insulating region or semiconductor substrate towards ground fsG. If the equivalent resistance from the memory element +Q2 to the ground line G at this time is R, the potentials at 8 points are
It rises to 2R.

On the other hand, if the potential during operation of word driver WD2 is V, the potential at point P rises to ■ with respect to the ground line, and 8
The potential difference between the point and the point P is α2R−V, a, (I
a2RV)> () Raishi x/Q? O emitter
When the write current increases until the base-to-base forward voltage VF) is reached, transistors Q'1 and Q? begins to draw current, the parasitic thyristor operates, and the write current is distributed. Therefore, a sufficient write current does not flow to the memory element, resulting in a write failure.

For example, write current 1 = 100m, transistor Q
Current amplification factor α2 of 'z = o, os, equivalent resistance R from the storage element to the ground line = 5000, potential during operation of the word driver WD is O, SV, and v of the transistor QT.
If l is 0.8v, the potential difference between point 8 and point P is I
α, R-V=2V, VFo of transistor QT, 8
V, and the parasitic thyristor easily operates.

Therefore, an object of the present invention is to provide a junction destruction type PROM which has a simple structure and which enables reliable programming by eliminating the parasitic thyristor that moves between memory elements.

[Means for solving the problem] The junction breakdown type FROM of the present invention has a memory element at the intersection of a plurality of word lines and bit lines.
- a plurality of strip-shaped collector regions of opposite conductivity type provided on a conductivity type semiconductor substrate; and a strip-shaped collector region of high impurity concentration of opposite conductivity type buried between the semiconductor substrate and the collector region; a buried layer, a band-shaped high impurity concentration insulating region of one conductivity type buried in the semiconductor substrate between each of the collector regions, and a plurality of insulating regions of one conductivity type provided in a line in each of the collector regions. a pace region; emitter regions of opposite conductivity type provided within the pace region;
a substrate electrode provided in the insulating region for extracting a semiconductor substrate potential; the collector electrode in the collector region serves as a word line, the emitter electrode in the emitter region serves as a bit line; and the substrate electrode serves as a ground line. At least one substrate electrode is connected to the substrate.

[Effect]

As described above, the present invention has the effect of eliminating parasitic thyristors between the memory elements because the substrate electrode connected to the ground line is provided near the memory elements.

That is, according to the present invention, since the distance from the memory element to the ground line is short, the equivalent resistance of the insulating region and the semiconductor substrate from the memory element to the ground line is small, and the write current in the insulating region and the semiconductor substrate is small. Even if some leakage occurs and is absorbed by the ground line, the increase in potential with respect to the ground line is small and the parasitic thyristor does not operate. Most of the write current
It can be programmed (written) stably and reliably.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a main part of an embodiment of a junction breakdown type PROM of the present invention, and FIG. 2 is a partial sectional view thereof.

In this embodiment, a plurality of word lines Wl, W and a bit line Bl
, B, in a junction breakdown type FROM having memory elements Q11-Q182 at the intersections with the semiconductor substrate 1 and the collector regions 4, a plurality of band-shaped N-type collector regions 4 provided on the P-type semiconductor substrate 1, and the semiconductor substrate 1 and the collector regions 4 a strip-shaped N+ type collector buried layer 2 buried between the collector region 4, a strip-shaped P-type insulating region 3 buried in the semiconductor substrate 1 between the collector region 4, and a strip-shaped N+ type collector buried layer 2 buried between the collector region 4 and the collector region 4; Multiple Pfs provided in a row
i base region 6, an N-type emitter region 7 provided within the base region 6, and an N-type emitter region 7 provided within the insulating region 3.
The collector electrode 8 in the collector region 4 is connected to the word line W,
, W, the emitter electrode 7' in the emitter region 7 is connected to the bit lines B1 to B6, the substrate electrode 9 is connected to the ground line G,
Five substrate electrodes 9 are provided, and the ground line G is connected to the word line W.
, , W, and are arranged parallel to each other.

That is, in this embodiment, the collector electrode 8 in the collector region 4, the emitter electrode 7' in the emitter region 7, and the substrate electrode 9 in the insulating region 3 are arranged in the memory area in the chip pattern layout diagram shown in FIG. Word lines W1 . W, is configured to be parallel to n.

As described above, in this embodiment, since the ground line is located near the memory element, the distance from the memory element to the ground line is short, and therefore the equivalent resistance R from the memory element to the ground line is small, and the insulation area is small. Even if a part of the write current leaks to the semiconductor substrate 1 and the semiconductor substrate 1, the increase in potential with respect to the ground line is small and the parasitic thyristor does not operate.

For example, from the equivalent circuit in Figure 8), the write current I
=100mA,) Current amplification factor α2 of transistor Qt = Q
, l, equivalent resistance R'=500, word dry, <-WD
If the operating potential of transistor QT is 0.5v1 and 0.8v, then the potential difference between point 8 and point P is Ia2B
'-V=OV and fk? ), the vF of the transistor QT is much lower, and the parasitic thyristor does not operate.

In this manner, in this embodiment, since the parasitic thyristor does not operate, most of the write current can be passed to the selected memory element, making it possible to perform stable and reliable programming (fIIF writing).

In this example, the case where there is one ground line and five substrate electrodes is shown, but this is due to the distance at which the parasitic thyristor does not operate depending on the equivalent resistance from the memory element to the ground line. , and the number of substrate electrodes in the memory element matrix can be freely selected. FIG. 3 shows an embodiment in which only one substrate electrode is provided.

Therefore, in the present invention, at least one substrate electrode can be provided.

In addition, in the above embodiment, for convenience of explanation, the bit line,
Although limiting the number of word lines, storage elements and ground lines,
It is clear that the present invention is not limited to these. Furthermore, in the above description, a P-type semiconductor substrate is used, but the same applies when an N-type semiconductor substrate is used.

〔Effect of the invention〕

As explained above in detail, the junction breaking type FRO of the present invention
M controls the operation of the parasitic thyristor by providing at least one substrate electrode in the memory element matrix and by providing the ground line connected to the substrate electrode in parallel with the word line connected to the collector electrode. This has the effect that it is possible to write (program) the memory element stably and reliably.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a main part of an embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3 is a plan view showing a main part of another embodiment of the invention, and FIG. A circuit diagram showing an example of a conventional junction destruction type FROM, FIG. 5 is a plan view showing the main parts, and FIG.
The figure is a partial cross-sectional view, FIG. 7 is a cross-sectional view of the chip plane, and FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Collector buried layer, 3... Insulating region, 4... Door door area, 5... ...Selective oxidation region, 6...
・Base region, 7...Emitter region, 7'
...Emitter electrode, 8. Axis...Collector electrode, 9...Substrate electrode, IO...Bit line, 11...Ground line, Bl sB+ ! ,”',
I3m------Bit line, G. Gl, G, ... ground wire, Qlr 鴫mn...
...Memory element, W*IW2. ”・, Wm ・= ・−
'7-wire, WD , WD2゜・-, WDn・・・・
-・Word driver. Agent: Susumu Uchihara, = '``j'',
::”';'t. 1.j −′−′°′ Atsushi left figure

Claims (2)

[Claims] (1) In a junction breakdown type PROM having a memory element at the intersection of a plurality of word lines and a bit line, a plurality of band-shaped collector regions of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a plurality of strip-shaped collector regions of an opposite conductivity type provided on a semiconductor substrate of one conductivity type; and a strip-shaped collector buried layer of high impurity concentration of opposite conductivity type buried between the collector region and the collector region, and a strip-shaped collector buried layer of high impurity concentration of one conductivity type buried in the semiconductor substrate between each of the collector regions. an insulating region, a plurality of base regions of one conductivity type provided in a line within the collector region, emitter regions of opposite conductivity type provided within the base regions, and emitter regions provided within the insulating region. a substrate electrode for extracting a semiconductor substrate potential, the collector electrode in the collector region is connected to a word line, the emitter electrode in the emitter region is connected to a bit line, and the substrate electrode is connected to a ground line, and at least one substrate electrode is provided. A junction-destructive PROM characterized by having the above-mentioned features. (2) A junction breakdown type PROM according to claim (1), wherein the ground line is provided parallel to the word line.