JPH03225864A - Programmable read only memory - Google Patents

Abstract

PURPOSE:To realize a large capacity of programmable read only memory(PROM), to which writing can be done with a relatively small current in simple structure by equipping it with an insulating film which breaks down and conducts electricity when specified voltage is applied between a word line and a column line. CONSTITUTION:This is equipped with a word line 1, a column line 2, a diode 3a, and an antifuse 4a, and the diode 3a and the antifuse 4a are connected in series to constitute a memory cell 5a of one bit, and this is connected between the word line 1 and the column line 2. And a thin insulating film 17, which constitutes the antifuse 4a, becomes conductive when its insulation is broken by applying relatively large voltage. This insulation breakdown is so-called voltage breakdown, and this can be done with a relatively small current. Since it shares one diffusion layer of the diode 3a with one electrode of the antifuse 4a, the occupancy per bit is small, and it possible to elevate packaging density. Hereby, a PROM where writing can be done with a relatively small current and capacity enlargement can be done, can be gotten.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention is applicable to programmable read-only memories, generally referred to as FROM, and in particular to unused (a)
The present invention relates to a destructible programmable read-only memory using the RIFUSE technology.

<Prior art> Destructive programmable read-only memory (rP)
ROMJ (referred to as ROMJ) has been known in the past as a junction destruction type and a fuse destruction type, and FIGS. 5 and 6 show equal division paths of the respective memory cells. The junction breakdown type shown in Fig. 5 has two diodes D, , D connected in series in opposite directions, and no current will flow in this state.
Information is written by passing a large current during writing to destroy the diode in the opposite direction, creating a short circuit.

In addition, in the fuse destruction type shown in Figure 6, one diode D
It consists of a series circuit consisting of a fuse F made of metal such as nichrome, and a fuse F made of metal such as nichrome. During writing, information is written by flowing a large current to blow out the fuse F and turning it off.

<Problems to be Solved by the Invention> In any of the above-mentioned conventional techniques, a large current is required at the time of writing. For this reason, bipolar technology capable of driving large currents is required, and as a result, junction-ruptured or fuse-ruptured FROMs have a lower degree of integration than other types of memories made with MO5 technology.

This invention focuses on these problems and develops an FR that allows writing operations to be performed with a relatively small current and also allows for large capacity storage.
It is a noni thing made for the purpose of providing OM.

<Means for Solving the Problems> In order to achieve the above-mentioned object, the FROM of the present invention has a memory cell connected between a word line and a column line,
This memory cell has one diode connected in series and an untifuuse, and the diode is made of one electrode on the untifuuse side or a diffusion layer formed by diffusing impurities into the semiconductor substrate. The use is made of an insulating film sandwiched between the diffusion layer and an electrode provided on the diffusion layer, and having a thickness that causes dielectric breakdown and conduction when a predetermined voltage is applied between the word line and column line. It is characterized by becoming.

<Operation>> The thin insulating film constituting the anti-fuse is dielectrically broken down and becomes conductive by applying a relatively large voltage. This dielectric breakdown is a so-called voltage breakdown, and can be performed with a relatively small current. Furthermore, since one diffusion layer of the diode is shared with one electrode of the anti-fuse, the area occupied by one bit is small and it is possible to increase the mounting phase change.

<Example> Hereinafter, the FROM of the present invention will be explained in detail with reference to an example.

FIG. 1(a) shows an equivalent circuit of a FROM memory cell of the first embodiment. l is the word line, 2 is the column line,
3a is a diode, 4a is an untied fuse, and the diode 3a and the untied fuse 4a are connected in series to form a 1-bit memory cell 5a, which is connected to the word line l.
and column line 2.

FIGS. 1(b) and 1(c) show this memory cell 5, respectively.
The plane and cross section of a are shown. The diode 3a is made up of a PN junction between an N diffusion layer 11 and a P+ diffusion layer 12, and the word line 1 is made of metal lO. The metal 10 and the P" diffusion layer 12 are connected through a contact portion 13. On the other hand, the untie fuse 4a is connected to one diffusion layer 11 of the diode 3a.
A thin insulating film 17 is sandwiched between the conductive polysilicon 16 and the conductive polysilicon 16. The conductive polycone 16 directly serves as one electrode of the anti-fuse 4a, and also serves as the column wire 2. Incidentally, in order to lower the resistance of the column wire 2, a structure such as Soricite, in which metal is attached on top of polynolyric material, may be used. 14 is an insulating oxide film, and 15 is a P layer of the substrate.

In this way, since one diffusion layer 11 of the diode 3a is used as one electrode of the untied fuse, the area occupied per pit can be reduced and the mounting phase change can be increased.

FIG. 2(a) shows an equivalent circuit of the memory cell PRO"vl of the second embodiment. As shown in this equivalent circuit, a tie-out 3b is connected between the word line l and the column line 2. A> type fuse 4b is connected in series to form a 1-bit memory cell 5b.As shown in FIGS. 2(b) and 2(c), this memory cell 5b has a diode 3b It is composed of a PN junction between a P diffusion layer 21 and an N' diffusion layer 22, and the word line 1 is composed of a metal 20.

The metal 20 and the N" diffusion layer 22 are connected through a contact portion 23. On the other hand, the untied fuse 4b is connected to the diode 3.
A thin insulating film 27 is sandwiched between one of the diffusion layers 21 and the conductive polysilicon 26. The conductive polycone 16 directly serves as one electrode of the anti-fuse 4b, and also serves as the column wire 2. Note that, similarly to the first embodiment, in order to lower the resistance of the column wire 2, a structure such as Soricite, in which metal is attached on top of polysilicon, may be used.

24 is an insulating oxide film, and 25 is an N layer of the substrate.

FIG. 3(a) shows an equivalent circuit of a FROM memory cell of the third embodiment. As shown in this equivalent circuit, a Schottky barrier diode 3C and an anti-fuse 4c are connected in series between a word line 1 and a column line 2 to form a 1-bit memory cell 5C. And Figure 3 (
As shown in (b) and (c) of the same figure, this memory cell 5
A Noyosotokyi diode 3c is composed of an N diffusion layer 31 and an anode electrode metal 32. 33 indicates an interface between the N diffusion layer 31 and the anode electrode metal 32.

The word line 1 is made of metal 30 and is electrically connected to an anode electrode metal 32. On the other hand, the anti-fuse 4c is constructed by sandwiching a thin insulating film 37 between the N diffusion layer 31 of the multilayer barrier diode t'' 3c and the conductive polysilicon 36.

The conductive voltine silicone 36 directly serves as one electrode of the anti-fuse 4c, and also as the column wire 2. A silicide-like structure may be used as in the second embodiment. 34 is an insulating oxide film, and 35 is a two-layer substrate.

Note that when the Nyoyot key barrier diode 3c is used in this manner, there is no minority carrier accumulation phenomenon as in the case of a PN junction diode, and high-speed operation is possible.

Figure 4:1. i shows an example of the overall system configuration of a PROM equipped with the above-mentioned memory cells 5a, 5b, or 5c. Memory cell matrix 100 is arranged in the row direction.

A plurality of word lines 1. column lines 2, and these word lines 1. The memory cells 5a, 5b, or 5c are arranged in a matrix at locations where the column lines 2 intersect. 101 is a row address decoder, and 102 is a column address decoder and sense amplifier. Memory cells are selected manually using A o = A n addresses, and 8 hits are output Q. - Q7 is obtained.

The write operation will be explained using the memory cell 5c as an example. Untifuuse 4 with no writing in progress
C is in an off state in which no current flows. When writing, a voltage considerably higher than the voltage for a normal read operation is applied between the word line 1 and the column line 2. For example, if the read operation voltage is 5V, a voltage of 18V is applied. By applying this voltage, the thin insulating film 37 is dielectrically broken down, and as a result, the N diffusion layer 31 and the conductive polysilicon 36 are brought into a conductive state (on state).

<Effects of the Invention> As is clear from the above, the FROM of the present invention has a memory cell connected between a word line and a column line,
This memory cell includes a diode and an anti-fuse connected in series, the upper third diode has one electrode on the anti-fuse side made up of a diffusion layer formed by diffusing impurities into a semiconductor substrate, and the anno-tifuse has a diffusion layer formed by diffusing impurities into a semiconductor substrate. It is sandwiched between a diffusion layer and an f-electrode provided on the diffusion layer, and is thin enough to cause dielectric breakdown and conduction when a predetermined voltage is applied between the word line and column line. Write operations can be easily performed with a relatively small current.

However, it is possible to realize a large-capacity programmable read-only memory with a simple configuration that occupies a small area per bit and has a high implementation variation.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) respectively show the first embodiment of the present invention; a),
(b) and (c) are diagrams showing the equivalent circuit, planar structure, and cross-sectional structure of the PFeoNl memory cell of the second embodiment of the invention, respectively. ),
(c) is the FROM of the third embodiment of this invention, respectively.
FIG. 4 is a diagram showing the equivalent circuit, planar structure, and cross-sectional structure of the memory cell of 1. FRO of the second or third embodiment
FIGS. 5 and 6 are diagrams showing the configuration of the entire system of M, and are diagrams showing equivalent circuits of a conventional junction-breaking type and a fuse-breaking type FROM, respectively. l...word line, 2...column line, 3a, 3b...PN
Junction diode, 3c... Key barrier diode, 4 a, 4 b, 4 c... Untied fuse, 5 a, 5 b, 5 c=-memory cell, 1
0,20.30-,'Tal,II,12.2+,22.
31 ・Diffusion layer, 13.23...Contact part, 16,
26.36... Conductive Polycon, I 7,27.
37・Thin insulating film, 32・Anode electrode metal, 33・
··interface. Patent applicant Nyabu Co., Ltd. Agent
Patent attorney: 1 person above Figure 2 (0) Figure 2 (b) Figure 2 (c) 6 Figure 3 (0) Section 3 (C) S^ 4 Figure 0゜0゜Figure 5 Figure 6

Claims (1)

[Claims] (1) A memory cell is connected between a word line and a column line, and this memory cell includes a diode and an antifuse connected in series, and one electrode of the diode on the antifuse side is connected to a semiconductor substrate. The antifuse is sandwiched between the diffusion layer and an electrode provided on the diffusion layer, and becomes insulated when a predetermined voltage is applied between the word line and column line. A programmable read-only memory characterized by comprising an insulating film having a thickness that becomes conductive when broken.