JPS61231752A - Junction breakdown type prom - Google Patents

Abstract

PURPOSE:To eliminate a parasitic thyristor effect and facilitate ensured programming by a method wherein a collector region connected to word lines is divided into collector island regions each of which has at least one collector electrode by an insulating separation region. CONSTITUTION:Collector regions 12 are formed on a semiconductor substrate 11 like islands and an insulating separation region 13 is provided between the islands of the collector regions 12 to separate those island-shaped collector regions 12 electrically. 2-8 base regions 14 are provided in one island-shaped collector region 12 to form memory elements Q11-Qmn. Further, a collector 16 is provided at the central part of one island-shaped collector region 12 and connected to a word line W1, W2,... or Wn. Therefore, the insulating separation region is connected to grounding wires in all directions so that current paths are dispersed and an equivalent resistance R between the insulating separation region and the grounding wires is reduced significantly and the potential of the memory element against the grounding wires rises only a little and hence a parasitic thyristor does not operate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction destruction type PR,OM (programmable read-only semiconductor memory).

[Conventional technology]

Programmable destructive read-only semiconductor memory (hereinafter referred to as FROM) requires reliable writing of information. In order to reliably write this information, it is necessary to reliably select the memory element to be written to and to supply a stable current to that element.

Conventionally, this type of FROM is classified into two types based on differences in the formation of unit memory elements. One is the fuse type, which uses a fuse and one PN junction connected to it as a memory element, and writes information by blowing the fuse.
It is M. The other type uses an element including two PN junctions connected in opposite directions as a memory element, and these two
This is a junction destruction type P-type OM in which information is written by destroying one of the two PN junctions.

FIG. 2 is a circuit diagram showing a circuit configuration of a memory element portion of a conventional junction breakdown type FROM. Memory element q.

~Qmn is bit line BI J "t+"・"'t
Bm and word line W, , W, , -9-...,
A word driver WD1.Wn is provided at the intersection with word line WD1. WD...

WDn is connected.

Now, an attempt is made to write information to the memory element Qll.

In this case, 'first, bit line B1 and word line W1 are selected. Then, a write current is applied from the bit line Bl to destroy the emitter-base junction of the memory element Qll, and the word
Absorb into driver WD.

FIG. 3 is a schematic plan view showing the main part of FIG. 2. A strip-shaped collector region 2 is provided on a semiconductor substrate 1, and an insulating separation region 3 is provided between the strips of the collector region 2 to electrically isolate each strip-shaped collector region 2. Therefore, this insulating isolation region 3 extends in a strip shape parallel to the collector region 2. A plurality of base regions 4 are provided in the collector region 2, and an emitter region 5 is provided in the base region 4, so that the memory elements Q1□ to Qff
lrl is formed. Furthermore, a collector electrode 6 is provided for every 2 to 8 memory elements, and a word line W.

It is connected to Wl, -...-Wn. Further, the emitter regions 5 of the memory elements Qll to Qmn are connected to the bit lines B, , B, . . . l B via the emitter electrodes.
connected to m.

[Problem that the invention seeks to solve]

FIG. 4 is a block diagram of this 280M.

A ground line 8 is arranged to surround the memory element matrix 7. Here, the strip-shaped insulating isolation region 3 in FIG. 3 is connected from the matrix 7 of memory elements to the left and right ground lines 8, as shown in the figure.

For example, if we consider a memory element in the center of the memory element matrix 7, such as point ■, it is far from the left and right grounding wires 8, so the distance of the insulation separation region 3 from point ■ to the grounding wire 8 is very long. Therefore, at point (3), the resistance of the insulation isolation region 3 up to the ground line 8 becomes extremely large. In this case, when writing information to the memory element at this point (2), a parasitic thyristor effect (parasitic pn pn effect) works. This mechanism will be briefly explained using the circuit shown in FIGS. 5(a) and 5(a). - Select bit line B11 and word line W and try to write information into storage element Qtz. At this time, for example, the adjacent word line W! It is assumed that there is a written memory element Qtt at the intersection of the bit line B1 and the bit line B1 (FIG. 5(a)).

In this case, the equivalent circuit is shown in FIG. 5 (bl).

In other words, between the bit line B1 and the word line W2, the storage element Q
Bow l in parallel with 1□(=D+Q'l!)! Oyohi thyristor T is connected.

Write current IW from bit pJBl to storage element Q+2
flows and is absorbed into the word driver WD. At this time, the collector current Iwα1. (α, 2 is Q10.
(current amplification factor) flows toward the ground line G through the isolation region or the semiconductor substrate. Here, memory element Q12
When the equivalent resistance from the ground line G to the ground line G is R, the potential at the 0 point increases with respect to the ground line G by an error α, 2. On the other hand, if the potential during operation of the word driver WD is -, then 0
The potential at the point is VW with respect to the ground line G. Therefore, the potential difference between the 0 point and the 0 point is IWα1 - vw, and the write current I,, 73E (1-a,, u-vw)
)V, (V, HAfI!J, x, riT's forward voltage), Q'tt and T start to draw current, the parasitic thyristor operates, and the write current error is dispersed. be done. As a result, a sufficient write current cannot flow through the memory element to which data is to be written, resulting in a write failure.

For example, in FIG. 4, the point ■ is located in the center of the memory element matrix 7, so the left and right ground +1!8
The length is very long. Here, layer resistance ρ of insulation isolation region 3 = 50 Ω/ro, width of insulation isolation region = 8 μm2
If the length of the insulation separation region from point ■ to grounding wire 8 is 1■, then the grounding from point ■ is 3125Ω, and the resistance r' from point ■ to the grounding wire via the semiconductor substrate is 500Ω. Equivalent resistance from element to ground u= r m
r'/(r+r')=431Ω. At this time, for example, the writing current is... = 1 o o mho
Current amplification factor a of Q'tt 1□='0.05° Potential VW during operation of word driver WD = 0.5V.

When the VF of the thyristor T is 0.8V, Fig. 5 (b
) The potential difference between the 0 point and the 0 point is Iwα12”-1 in VW
．． 7, which greatly exceeds the vF of thyrisk T, 0.8v, and the parasitic thyristor easily operates.

An object of the present invention is to create a junction destruction type FROM that enables reliable programming by eliminating the parasitic thyristor effect (parasitic pn pn effect) that acts between memory elements with a simple configuration.
Our goal is to provide the following.

[Means for solving problems]

The junction breakdown type P-OM of the present invention includes a plurality of collector regions of opposite conductivity type provided on one principal surface of a semiconductor substrate of negative conductivity type, and a high impurity probe of one conductivity type provided between each of the collector regions. a plurality of storage elements formed by providing a plurality of base regions of one conductivity type in one row in the collector region and emitter regions of opposite conductivity type in the base regions; In a junction breakdown type FROM, the collector electrode includes a collector electrode connected to a word line and provided at every plurality of memory elements formed in the memory element, the collector region being connected to at least one word line. Each of the memory element groups having a plurality of memory elements is divided into collector island regions by the insulating two regions.

[Effect]

As described above, the present invention has the following advantages: By separating the collector region connected to the word line into a collector island region having at least one collector electrode using an insulating separation region,
The isolation region is connected to the ground wire on all sides, unlike the conventional method in which the isolation region is connected to the ground wire at both ends thereof. As a result, the current flowing through the insulation isolation region flows to the ground line through multiple paths. Therefore, the equivalent resistance of the insulation separation region from the memory element to the ground line is small, and even if a part of the write current leaks to the semiconductor substrate and is absorbed by the ground line, the rise in t with respect to the ground line is small and the parasitic Si risk (parasitic pnpn) does not work.

Therefore, most of the write current can be passed to the selected memory element, allowing stable and reliable programming (writing).

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view showing essential parts of an embodiment of the present invention. Collector regions 12 are provided in the form of islands on a semiconductor substrate 11, and insulating isolation regions 13 are provided between the islands of the collector regions 17 to electrically isolate the respective island-shaped collector region structures 2.

Further, by providing 2 to 8 base regions 14 in one island-shaped collector region 12 and providing an emitter region 15 in this base region 14, the memory elements Qjl to Q m
form n. Further, this emitter region 15 is connected to the bit line B1°Bt +..., via the emitter electrode.
BmK connect. Furthermore, one island-like collector region 1
A collector electrode 16 is provided at the center of the word line W.
,,W,,..., connect to Wn.

Comparing the plan views of this embodiment and the conventional example shown in FIG. is formed in a grid pattern.

For this reason, the equivalent resistance from the memory element to the ground line has conventionally shown a high value because of the long distance, but according to this embodiment, the distance does not become long, so it takes a low value. In other words, conventionally, the connection between the insulation isolation region and the ground wire was only bidirectional, but according to this embodiment,
Since they are connected on all sides, the current paths can be distributed, and the equivalent resistance R from the storage element to the ground line is significantly reduced.

For example, in Fig. 4, point ■ is where the length of the insulation separation region from point ■ to the ground wire is conventionally very long, so the resistance r of the insulation separation region from point ■ to the ground wire is large, and the parasitic thyristor easily operates. did. However, according to this embodiment, since the insulating valve m region is connected to the ground wire on all sides, the resistance r from point 2 to the ground wire becomes small.

Applying this to the case of the conventional example in Fig. 4, if the resistance r (DIIIil) from point ■ to ground M is /10, that is, 313Ω, then the resistance from point ■ to the ground wire via the semiconductor substrate When r'=500Ω, the equivalent resistance R from the unit storage element to the ground line is R= r °r'
/(r+r') = 192Ω.

At this time, for example, the write current Iw=100mA.

Q'1. The current amplification factor α1. =0.05 word driver! Potential VW during operation of WD = 0.5v, v of thyristor T
When F is set to 0.8v, the 0 point and 0 shown in Figure 5(b)
The potential difference at the point is ξα1. R-Vw=: 0846V, which is less than 0.8V, which is the vF of the thyristor T, so the parasitic thyristor does not operate.

Therefore, according to the present invention, it is possible to prevent the parasitic thyristor effect (parasitic pn pn effect) that acts between memory elements with a simple configuration, and to enable reliable programming. is obtained.

In the above embodiment, the collector island region is provided for each collector electrode, but the same effect of the present invention can be obtained even if a storage element group including two or more collector electrodes is provided in the same collector island region.

〔Effect of the invention〕

As explained above in detail, the junction breaking type FRO of the present invention
M reduces the resistance between the substrate potential and the storage element by dividing the collector region connected to the word line into collector island regions each having at least one collector electrode using an insulating isolation region. This has the effect of preventing the parasitic thyristor effect (parasitic pnpn effect) and allowing stable and reliable writing (programming) to the memory element.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing the main parts of an embodiment of the present invention;
Fig. 2 is a circuit diagram showing the main parts of a conventional example, Fig. 3 is a schematic plan view showing the main parts of a conventional example, Fig. 4 is a schematic diagram showing the chip of a conventional example, and Fig. 5 Figures (a) and (b) are explanatory diagrams of the parasitic thyristor effect of the junction breakdown type PR and OM. 11... Semiconductor substrate, 12... Collector region, 13... Insulating isolation region, 14...
... Base region, 15 ... Emitter region, 16
...Collector electrode, B1-B, ...Bit line, Qtt-Q? 2... Memory element, W. W2...Word line. Figure 3

Claims (1)

[Claims] a plurality of collector regions of opposite conductivity type provided on one principal surface of a semiconductor substrate of one conductivity type; a high impurity concentration insulating isolation region of one conductivity type provided between the respective collector regions; a plurality of memory elements formed by providing a plurality of base regions of one conductivity type in one row and emitter regions of opposite conductivity type in the base regions, and a plurality of memory elements formed in each row of In a junction breakdown type PROM including a collector electrode provided and connected to a word line, the collector region includes the insulating isolation region for each storage element group having the collector electrode connected to at least one word line. A junction-destructive PROM characterized by being divided into collector island regions.