JPH04186671A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent effects of access to one memory cell on adjacent cells by arranging first and second signal lines, respectively, along rows and columns of memory cells, allotting a plurality of the first signal lines for one row of memory cells, and connecting one of the first signal lines to a plurality of memory cells that are not adjacent. CONSTITUTION:A pair of word lines WL are arranged between two corresponding rows of memory cells 10. The word lines are twisted in such a manner that each of them is connected alternately to memory cells in opposite rows on both sides. When one of the word lines selected, therefore, it accesses all the even cells of one row and all the odd cells of the other row. On the other hand, bit lines BL are arranged straight along columns of memory cells 10, and each is connected with a plurality of cells in parallel. Therefore, simultaneous access to adjacent cells is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a RAM I2D semiconductor memory device,
In particular, it relates to the wiring structure of the memory cell section.

(b) Prior Art FIG. 6 is a block diagram of a static type RλM memory cell section, and FIG. 7 is a circuit diagram of each memory cell.

Memory cells (10) arranged in row and column directions are:
Consists of four MOS transistors (1) to (4) and two resistors <5) (6), MOS transistor (1)
The drain and gate of (2) are connected to each other, the drain is connected to a power supply via resistors (5) and (6), and the source is grounded to form a bistable flip-flop. Furthermore, MOS ) transistors (1) (2
) is connected to the bit line BL via a MOS transistor <3) (4), and a MOS transistor is connected to the word line WL.
The gates of transistors (3) and (4) are connected.

These memory cells (10) are arranged facing each other with two word lines in between, and the M of the opposing memory cells (10) is
OS transistors (3) and (4) are commonly connected to a pair of bit lines BL.

A plurality of memory cells (lO) are connected in parallel to the pair of bit lines BL, and one of the memory cells (10) is designated according to address information given to the word line WL. Further, a sense amplifier is connected to the bit line BL to detect a change in the potential of the bit line BL according to the state of a designated memory cell (10), and the data stored in the memory cell (10) is determined. Therefore, a specific memory cell (10) is designated according to the address information, and data stored in the designated memory cell (10) is read out through the sense amplifier.

FIG. 8 is a plan view showing the structure of the connection portion of the word line WL and bit line BL to the memory cell (10), and FIG. 9 is a cross-sectional view taken along the line X--X.

On the surface of the P-type semiconductor substrate (11), a pair of gate electrodes ti (12>, which will become word lines WL) are provided via an insulating film (13), and with this gate electrode (+2) as a mask, N
A MOS type diffusion region (14) is formed by a self-alignment line, and the memory cell (10) and the bit line BL are connected by this diffusion region (14) and a gate electrode (+2>).
) transistors (3) and (4) are constructed. Then, the wiring (15) that becomes the bit line BL is perpendicular to the gate electrode IM (12) and along the diffusion region (14), the gate electrode i (
12) A contact hole (16) is formed on the diffusion region (14) formed between the pair of gate electrodes (12).
). Therefore, the memory cell (10) that is continuous with the diffusion region (14) is a MOS transistor (3).
) (4) to the bit line BL.

(c) Problems to be Solved by the Invention In the memory device as described above, a plurality of memory cells (10) arranged in the row direction are simultaneously connected to each bit line BL by selecting a word line WL. Therefore, there is a risk that adjacent memory cells (10) may be affected by each other and cause malfunctions. Specifically, current may flow simultaneously through the ground line provided in common for each row. Possible causes include ground potential fluctuations, etc.In particular, in memory devices that have become highly integrated due to increased capacity, the arrangement spacing between memory cells (10) becomes narrower, so the mutual influence between memory cells (10) may occur. It becomes easier to receive.

Therefore, an object of the present invention is to operate each memory cell so that there is no influence between adjacent memory cells.

(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of memory cells are arranged in row and column directions, and the memory cells along the row and column of
and a second signal line are arranged and connected to each memory cell, and the row and column of the memory cell are specified by selection of the first and second signal lines, the semiconductor memory device comprising:
The plurality of first signal lines are associated with one row of memory cells, and one first signal line specifies the memory cells at appropriate intervals.

(E) Effect According to the present invention, memory cells arranged in the row direction operate simultaneously at appropriate intervals, and since adjacent memory cells do not operate simultaneously, mutual influence between memory cells is reduced. It becomes difficult to receive.

(f) Example Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this figure, the memory cells (10) themselves are the same as in FIG. 6, and a plurality of them are arranged in the row and column directions.

The feature of the present invention is that the pair of word lines WL are
Memory cells (10
) are connected alternately. That is, two rows of memory cells (10) are associated with a pair of word lines WL, and the memory cells (10) of each row and each word line WL are alternately connected, so that one word line WL is The configuration is such that the memory cells (10) in even columns of one row and the memory cells (10) in odd columns of the other row are specified at the same time by selection.

On the other hand, the bit line BL is connected to the memory cell (10
) are formed in a straight line along the rows of memory cells (
10) are connected in parallel.

FIG. 2 is a plan view showing the structure of the connection portion of the word line WL and bit line BL to the memory cell (10), and FIG.
aHb) are a cross-sectional view along the line X-X and a cross-sectional view along the Y-Y line, respectively.

On the surface of the P-type semiconductor substrate (21), there is one word line W.
The first layer gate electrode (22) that is L is an insulating film (23)
It is formed in a meandering manner so as to correspond to the arrangement of the memory cells (10). In addition, an independent gate electrode (24)
is provided in parallel to the first layer gate electrode (22). Then, using these gate electrodes (22N24) as a mask, an N-type diffusion region (25) is formed by self-alignment.
and its gate electrode (22>(24>) constitutes a MOS transistor (3)<4) that connects the memory cell (10) and the bit line BL.Furthermore, the other word line W
The gate electrode (26) of the second layer which becomes L is connected to the insulating film (23
) is formed so as to overlap the independent gate electrode (24). This gate electric 1'! (26) is an insulating film (
It is connected to an independent gate electrode (24) through a contact hole (27) provided in (23), so that this gate electrode (24) operates as the gate of the MOS transistors (3) and (4). On this second layer gate electrode (26), a wiring (28) that will become the bit line BL is formed along the diffusion region (25), and is passed through the contact hole (29) of the insulating film (23) to the gate electrode (28). 22>(
24) to the diffusion region (25) between the two.

In this way, the word line WL is connected to the gate electrode (22
) By configuring (24) and (26), the word line W
It becomes possible to cross each word line WL, and it becomes possible to alternately connect one word line WL to memory cells (10) arranged on both sides thereof. Here, regarding the second layer gate electrode (26), since the film thickness of the insulating film (23) becomes thick and it no longer operates as a MoS transistor,
By providing an independent gate electrode (24), the first layer gate electrode (22) and the second layer gate electrode (26) are set to the same conditions.

FIGS. 4 and 5 are block diagrams showing other embodiments of the present invention.

A plurality of memory cells (lO) are arranged in row and column directions, and word lines WL and bit lines BL are arranged along the rows and columns of memory cells (10), respectively. Two word lines WL are respectively associated with the memory cells (10) in each row. (in the case shown in FIG. 5), or on both sides of the memory cell (10) (in the case shown in FIG. 5). Each memory cell (10) is alternately connected to two word lines WL associated with each row, and one word line WL connects the memory cells (10) in the row direction.
10) is specified every other time.

In this way, when two word lines WL are associated with the memory cell (10) in the - row, the number of memory cells (10) specified by one word line WL becomes half the number. However, this can be handled by doubling the arrangement of memory cells (10) in the row direction. Furthermore, by configuring one of the word lines WL of adjacent rows to be designated at the same time, it is also possible to designate every other memory cell (10) in two rows as in FIG. 1.

Effects of the Invention According to the present invention, since there is no need for adjacent memory cells to be designated and operated at the same time, the influence between memory cells is reduced, and the ground line is reduced due to the simultaneous operation of a plurality of memory cells. This reduces the potential rise in the power supply line and the potential drop in the power supply line. Therefore, malfunctions of various circuits can be prevented and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a sectional view of FIG. 2, FIGS. 4 and 5 are block diagrams of other embodiments of the present invention, and FIG. 6 is a block diagram of a conventional memory device. , FIG. 7 is a circuit diagram of the memory cell, FIG. 8 is a plan view of the specific structure of FIG. 7,
FIG. 9 is a sectional view of FIG. 8. (1) (2) (3) (4) ・・MOS) transistor, (5) (6)・resistance, (lO) ・・memory cell,
(11)(21)・・Semiconductor substrate, (12)(22)
(24) (26) Gate electrode, (13) (2
3>...Insulating film, (14) (25) Diffusion region,
(15) (28) --- Wiring, (16) (27) <
29) Contact hole.

Claims (3)

[Claims] (1) A plurality of memory cells are arranged in row and column directions, and first and second memory cells are arranged along the rows and columns of the memory cells.
A semiconductor memory device in which a plurality of signal lines are arranged and connected to each memory cell, and the row and column of the memory cell are specified by selection of the first and second signal lines, the plurality of first signal lines is associated with one row of memory cells,
A semiconductor memory device characterized in that the memory cells are designated by one first signal line at appropriate intervals. (2) A pair of said first signal lines are arranged between a pair of said memory cells arranged oppositely, and each memory cell is alternately connected to each first signal line. 2. The semiconductor memory device according to claim 1. (3) A claim characterized in that a pair of the first signal lines are arranged adjacent to the memory cell columns arranged in the row direction, and each memory cell is alternately connected to each first signal line. The semiconductor memory device according to item 1.