JP3208591B2 - Static RAM device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to the formation and connection of a word line in a static RAM (SRAM) device which simplifies an active area and facilitates element isolation.

[0002]

2. Description of the Related Art An SRAM device is known as a high-speed operation memory, and higher integration and higher speed have been attempted. FIG. 6 shows a circuit configuration of one memory cell in the SRAM device and a connection state of a word line and a bit line connected to the memory cell. In this SRAM device, nMOS driving transistors Q ₁ and Q ₂ , nMOS transfer transistors Q ₃ and Q ₄ , and a load L are connected as shown in the figure. One end of the load L is connected to a transfer transistor Q ₃ ,
Common connection point of the source Q drain and the driving transistor of ₄ Q _1, Q ₂ are connected to a (storage node), V _CC power source is connected to the other end. V _SS power supply to the drain of the driving transistor Q _1, Q ₂ are connected. Word line WL is transfer transistor Q
_3, is connected to the gate of Q _4, the bit line BL is connected to the source of the transfer transistor Q _3, inverted bit line * B operating at bit lines BL and opposite polarity
L (in the figure, a bar is shown above BL, but in this specification, an inversion is indicated by *, the same applies hereinafter).
It is connected to the source of the transistor Q _4. The gates of the transfer transistors Q ₃ and Q ₄ are connected in a crossing manner so as to form a flip-flop circuit.

A bit line BL and an inverted bit line * B
L means that data is written to or read from the driving transistors Q ₁ and Q ₂ functioning as flip-flop circuits via the transfer transistors Q ₃ and Q ₄ selected by the word line WL. Works. In the SRAM device, a plurality of the one memory cells are arranged in a matrix, and the word line WL and the bit line BL, the inverted bit line *
Data is written to a desired memory cell by selecting BL, or data is read from the memory cell.

FIG. 7 shows one of the SRAM devices shown in FIG.
A plan view of a memory cell is shown (for example, NIKKEI
MICRODEVICES, September 1988, page 128). The dimensions of this memory cell are 5.2 μm × 7.9 μm
It is. The driving transistors Q ₁ , Q ₂ are formed at slightly diagonal positions, and the transfer transistors Q ₃ , Q ₂
Q ₄ is formed at a diagonal position parallel to the transistors Q ₁ and Q ₂ . The symbols Q ₁ ,
Active regions are formed near the gate portions denoted as Q ₂ , Q ₃ , and Q ₄ . LOC between the bold lines
An OS is formed. These driving transistors Q ₁ and Q ₂ and transfer transistors Q ₃ and Q
_The word line WL is formed on the first layer above the layer ₄ , and the _Vcc power supply line layer is formed on the second layer. Further, a bit line BL and an inverted bit line * BL are formed thereon. A square or rectangular figure of the cross mark indicates a contact portion.

[0005] Bit line BL and inverted bit line * B
L is formed substantially in parallel. A word line WL is formed substantially orthogonal to the parallel bit line BL and inverted bit line * BL. As shown in FIG. 6, the number of word lines WL is one.
The first layer is made of polycrystalline silicon (polysilicon, PC) so as to pass over the gates of the transistors Q ₃ and Q ₄ . The driving transistors Q ₁ and Q ₂ are formed at slightly diagonal positions, and a load L is formed between the driving transistors Q ₁ and Q ₂ and the _VCC power supply layer. The _Vcc power supply layer is formed of polysilicon as the second layer,
pMOSTFT of p ^- form (type) are formed by diffusion layers.
share a gate electrode and pMOSTFT the driving transistors Q ₁ and Q _2.

[0006]

In this SRAM device, since one word line WL from the row decoder is connected in common to the gates of the transfer transistors Q ₃ and Q ₄ as it is, the word line WL is The transfer transistors Q ₃ and Q ₄ formed at positions deviated from the direction of the word line WL are bent in accordance with the gate positions. Further, the driving transistors Q ₁ and Q ₂ constitute a flip-flop circuit, and it is necessary to provide a cross wiring for these gates.
As a result, word line WL is applied to one column of memory cells.
In the conventional SRAM device having only one device, there is a problem that the element arrangement and its separation become complicated, and particularly, the shape of the active region becomes fine and complicated, and it becomes difficult in the element separation process by LOCOS. That is, the LOCOS design rule is difficult due to lack of symmetry of the element arrangement. In addition, the connection state of the word line WL, bit line BL, and inverted bit line * BL becomes severe, the dimensions are close to each other, and the degree of integration cannot be improved. Further, the load L is connected to an asymmetric position, and lacks stability in reading operation and the like.

The above problems are caused by other SRAM devices such as an E / R type SRAM device and an E / D type SRAM.
The same applies to devices and CMOS SRAM devices. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve problems related to element formation arrangement of a memory cell of an SRAM device and wiring of a word line or a bit line and an inverted bit line for the memory cell.

[0008]

According to the present invention, each of the input terminals is connected to a positive and negative (inverted) bit line, and each of the control terminals is connected to a single word line. First and second transfer transistors connected to first and second sub-word lines for supplying a selection signal and having output terminals connected to the first and second nodes, respectively, and load terminals each connected to the first and second sub-word lines. First and second driving transistors connected to the first and second nodes and having respective control terminals connected to the second and first nodes to form flip-flop circuits; A first and a second load connected to respective load terminals of the first and second driving transistors via a second node; And a bit line of negative polarity is disposed in parallel and close to each other, and the first and second sub-word lines are substantially orthogonal to the bit line, and are formed on a layer different from the bit line at a predetermined interval. The first first and second sub-word lines are disposed in parallel with each other and substantially in the center of the internal region between the first and second sub-word lines. And a power supply contact portion for grounding the second drive transistor, wherein both sides of the power supply contact portion for ground inclined at approximately 45 ° with respect to the bit line or the sub-word line and the positive and negative polarity bits are provided. The first and second driving transistors are disposed below the line, and the first driving transistor, the first node, and the first transistor are arranged along the positive bit line. Transfer transistors are arranged side by side, the first transfer transistors are arranged below or near the first sub-word line, and the second drive transistors are arranged along the negative bit line. A second node and said second transfer transistor are arranged side by side;
The second sub-word line is located at or below the second sub-word line.
And the first and second loads are respectively disposed near the first and second nodes at rotationally symmetric positions of the grounding power contact section. Statec RA featuring
An M device is provided.

According to the planar arrangement of the static RAM device of the present invention, a pair of driving transistors having a flip-flop circuit configuration are formed facing each other around a grounding power supply contact portion, and these driving transistors are arranged opposite to each other. A pair of transfer transistors are formed at opposing positions on the outside, and contact portions of a pair of bit lines operating with opposite polarities are formed at opposing positions near respective input points of the pair of transfer transistors. A sub-word line branched from a common word line is disposed in parallel at a position substantially orthogonal to these bit lines and passing above the control units of the pair of first transfer transistors. In this way, the word lines are
Branching into a pair of sub-word lines driven in phase
When used, transfer transistor gaming can be easily performed.
Can be connected to the active area, and the active area can be
Be pure. And the source of the transfer transistor
Bit line contact, inverted bit line contact
Connection with the transfer unit is easy.
The connection between each drain of the
There is no use. That is, the first and second sub-word lines
No connection with bit line and inverted bit line
The driving transistor and the second driving transistor are
First and second sub-word lines and bit lines;
First and second trucks with connections to inverted bit lines
Can be formed inside the transfer transistor,
The circuit arrangement of the memory cells is simplified. Furthermore the first and
The second driving transistor forms a flip-flop circuit.
Requires cross wiring and is connected to the load.
The formation positions of these wirings and loads are determined by the first and second toes.
Inside the transfer transistor, the memory cell
The circuit configuration of the body is simplified and scalable, and its manufacturing process
Will also be easier. Load connected to the node, eg, T
The FT formation position is also a balanced position. Further
In addition, the active area can be simplified and LOCOS is impossible.
In addition, the element isolation process is also facilitated. And anti
Around bit line and bit line contacts
The bit contact pads located in
Can be provided.

[0010]

A control unit, for example, a word line WL connected to the gate of a MOS transistor is branched to a pair of transfer transistors constituting a memory cell, and a sub-word line branched from a word line driven in phase is connected to the control unit. By providing two (one pair), the elements constituting the memory cell can be arranged at substantially symmetric positions. That is, in the above static RAM device, a pair of driving transistors having a flip-flop circuit configuration are arranged inside the memory cell, and transfer transistors connected to the sub-word lines and the bit lines are opposed to the outside. Deploy. As a result, the pattern of the active region in the memory cell can be simplified, extra space can be removed, and the element isolation process can be facilitated.
Also, the sub-word lines are short-circuited at predetermined intervals by connection lines to eliminate potential differences and operation timing differences between the sub-word lines.

[0011]

FIG. 1 is a partial view of an SRAM device according to the present invention. The SRAM device shown in FIG. 1 includes memory cells MC _{11 to} MC ₁₃ and MC _{21 to} MC arranged in a matrix.
_23, MC ₃₁ with respect to MC _33, row decoder common word line WL1~WL3 connected to (not shown), respectively, a pair of sub-word lines WL1 _1: WL1 _2, W
L2 _{1 is} divided into WL2 ₂ and WL3 ₁ : WL3 ₂ and connected to the memory cell MC. A pair of bit lines and inverted bit lines BL1: * BL1, BL2: * BL2 connected to a column decoder (not shown).
BL3: * BL3 is the above-mentioned sub-word line WL1 ₁ : WL
_{1 2, WL2 1: WL2 2} , WL3 1: WL3 2 are connected so as to be perpendicular to the. The bit line BL and the inverted bit line * BL are the same as those shown in FIG. 6, but the configuration of the word line shown in FIG. 1 is such that, for each memory cell MC, a first sub-word line, for example, WL
1 ₁ and second sub-word lines, for example, WL1 ₂ 1
The difference is that two pairs are provided. The first sub-word line WL1 ₁ and the second sub-word line WL1
₂ is branched from a common word line WL1 connected to a row decoder (not shown), and is driven in the in-phase state.

[0012] 1 memory cell detailed circuit and the first sub-word lines WL1 ₁ near its MC of FIG. 1 in FIG. 2, the second sub-word lines WL1 _2, the bit lines BL, inverted bit line * BL connection circuit Is shown. This memory cell MC
Are a first driving transistor QN1 and a second driving transistor QN2, a first transfer transistor QW1 and a second transfer transistor QN1.
W2, a pair of loads L as loads of the driving transistors QN1 and QN2 are connected as shown. The gates of the first driving transistor QN1 and the second driving transistor QN2 are connected in an intersecting manner so as to constitute a flip-flop circuit for storing and holding data. First transfer transistor QW1
Is connected to the inverted bit line * BL, and its drain is connected to the gate of the first driving transistor QN1 at the node NB. The source of the second transfer transistor QW2 is connected to the bit line BL.
And its drain is connected to the gate of the second driving transistor QN2 at the positive storage node NA.

First transfer transistor QW1
The gate is connected to the first sub-word lines WL1 ₁ is the gate of the second transfer transistor QW2 are connected to the second sub-word lines WL1 ₂ is.
Drain of the first driving transistor QN1 and the second driving transistor QN2 is connected to the V _SS supply line. The first driving transistor QN1 and the second driving transistor QN2 are connected to loads L via nodes NA and NB, respectively, and the other ends of the loads L are connected to a _VCC power supply line.

Since the operation of the SRAM device shown in FIG. 2 is the same as the operation of the SRAM device described with reference to FIG. 6, the description of the operation is omitted.

[0015] Figure 3, Figures 1 and 2 the first sub-word lines WL1 ₁ branches the common word line WL from the row decoder shown in the second sub-word lines WL1 ₂
Element of the memory cell MC of the case in which the first sub-word lines WL1 ₁ and second sub-word lines WL
1 ₂ , bit line BL and inverted bit line * BL
FIG. 2 is a plan view showing a basic arrangement. A figure in which a cross mark is attached to a square figure indicates a contact portion.

A contact portion of the bit line BL is provided at the upper part of the drawing, and a contact portion of the inverted bit line * BL is formed at a position facing the lower portion of the center _VSS power supply contact portion. Between the bit line BL contact portion and the inverted bit line * BL contact portion, the first transfer transistor QW1
And a second transfer transistor QW2 are formed, and these transfer transistors QW1 and QW2
First driving transistor QN1 and the second driving transistor QN2 is disposed at a position facing each other across a V _SS power supply contact portion between. First sub word line W
L1 ₁ is arranged in a direction orthogonal to the bit line BL over the gate of the first transfer transistor QW1. The second sub-word lines WL1 ₂ are arranged in a direction perpendicular to the inverted bit line * BL on the gate of the second transfer transistor QW2. An active region 10 is formed as shown.

The gates of the first driving transistor QN1 and the second driving transistor QN2 are connected in an intersecting manner so as to form a flip-flop via a ground _VSS power supply contact portion. The drain of the first driving transistor QN1 and the drain of the second driving transistor QN2 are connected to a _VSS power supply contact located near the drain. First driving transistor Q
The source of N1 is connected to the drain of the first transfer transistor QW1 formed at an adjacent position, and the common connection position is the positive storage node NA. Similarly, the source of the second driving transistor QN2 is connected to the drain of the second transfer transistor QW2 formed at an adjacent position, and the common connection position is the negative storage node NB. Loads L each composed of a thin film transistor (TFT) are connected from the nodes NA and NB. The loads L are formed at upper and lower target positions and connected to a V _CC power supply unit (not shown).

The plan view shown in Figure 3 the sub-word line WL1 ₁ element and the first in the memory cell, a second sub-word lines WL1 _2, the bit line BL, the position is a position symmetrical inverted bit line * BL And face each other. Connected between the elements mutually adjacent in the memory cell MC, and the first sub-word lines WL1 _1, the second connection between the sub-word line WL1 _2, the bit line BL, is without waste line connection to the inverted bit line * BL And the pattern of the active area is simplified. In other words, the circuit arrangement shown in FIG. 3 has a structure that is reasonable from the viewpoint of the arrangement along the circuit shown in FIG. 2, the pattern of the active region can be greatly simplified, and the element isolation process is easy. And the design rules are simplified. Since the bit line BL contact portion and the inverted bit line * BL contact portion are separated from each other, the bit line contact portion and the inverted bit line contact portion can be made large. Since the TFT transistor as the load L is also formed at a balanced position, the problem relating to the instability of operation is solved.

A plan view of the circuit arrangement shown in FIG. 2 will be described more specifically with reference to FIG. The plan view shown in FIG. 4 is slightly different from the active area shown in FIG. 3 in the shape of the active area and is basically the same as FIG. 3 showing the basic plane. FIG. 2 illustrates a planar configuration that more specifically shows the drawing. A square figure shown by a cross mark indicates a contact portion. In this example, a polysilicon thin film transistor (T
FT). A _Vss power contact portion is formed at the center of the drawing. V _SS power supply contact portion slightly diagonal opposite inverted position Bit line around the * BL
A contact portion and a bit line BL contact portion are formed. Inverted bit line * Bit contact pad 101, bit line BL around BL contact part
Bit contact pad 102 around the contact portion
Is located. Inverted bit line * BL and orthogonal, inverted bit line * BL contact portion second word lines WL1 ₂ adjacent is placed. Similarly, orthogonal to the bit line BL, the first word line WL1 ₁ adjacent to the bit line BL contact portion is disposed.

[0020] the second lower sub-word lines WL1 ₂ is formed a second gate portion of the transfer transistor QW2 (indicated by symbol QW2) is the source of the transfer transistor QW2 is inverted bit line * B
The drain is connected to the node NB and the drain is connected to the L contact portion. The gate (indicated by the symbol QN1) of the first driving transistor QN1 is connected to this node NB. Drain of the first driving transistor QN1 is connected to the V _SS power contact portion. The source of the first driving transistor QN1 is connected to the load L via the contact of the node NA. The first is the gate of the first transfer transistor QW1 (indicated by symbol QW1) are formed in the lower portion of the sub-word lines WL1 _1, the source of the transfer transistor QW1 are connected to the bit line BL contact portion, The drain is connected to the node NA. The gate (indicated by the symbol QN2) of the second driving transistor QN2 is connected to this node NA. Second driving transistor Q
Drain of N2 is connected to the V _SS power contact portion. The source of the second driving transistor QN2 is connected to the load L via the contact of the node NB.

The sub-word line WL1 ₁ gate electrode and the first polysilicon of the first layer is a transistor, is formed as _two second sub-word lines WL1, grounding second layer polysilicon is formed over substantially the entire surface ( GND) line, and a third-layer polysilicon is used as a wiring between the gate electrode of the pMOS TFT, the nodes NA and NB as storage nodes, and the gate electrodes of the driving transistors QN1 and QN2. Constitute an active layer of the _Vcc power supply wiring and the TFT. The third layer of polysilicon doubles as the gate of the TFT and the wiring in the memory cell MC. Two third-layer polysilicon patterns are arranged 180 degrees point-symmetrically with respect to the _VSS power supply contact portion. V _CC power source wiring line traverses the central portion of the fourth layer is composed of polysilicon, the sub-word line WL1 _1, WL1 memory cells MC in the _second direction. A TFT transistor which is branched from the _Vcc power supply line and becomes a load L is formed, is connected to the third-layer polysilicon through a fourth-layer polysilicon contact portion, and further has a storage node N.
A, NB are connected. The bit line BL and the inverted bit line * BL are formed of a metal such as aluminum, and are connected to their respective contact portions.
The bit contact pads 101 and 102 are formed of a second-layer polysilicon formed by a self-aligned contact.

Also in this plan view, the first transfer transistor QW1 and the second transfer transistor QW2 are located almost opposite each other around the _Vss power supply contact portion, respectively, at the bit line BL contact portion and the inverted bit line. * BL near the contact portion is formed in the lower part of the first sub-word lines WL1 ₁ and second sub-word lines WL1 _2. To configure a flip-flop circuit, those gates are connected to nodes NA and NB.
While being cross-connected via a bit line BL and inverted bit line * BL from the outside, as well as the first sub-word lines WL1 ₁ and second sub-word line W
First driving transistor Q having no direct connection to L1 ₂
N1 and the second driving transistor QN2 are connected to the node N
V whose drains are connected between A and node NB
It is formed on both sides of the _SS power contact.

[0023] branches in this way the word line WL1 to the sub-word line WL1 ₁ a pair of driven in phase and WL1 ₂ and enables the arrangement can be easily connected to the gate of the transfer transistor QW1 and QW2, respectively, The active area is simplified. Further, it is easy to connect the sources of the transfer transistors QW1 and QW2 to the bit line BL contact portion and the inverted bit line * BL contact portion, and the respective drains of the transfer transistors QW1 and QW2 and the nodes NA and N
The connection with B is also direct and has no waste. That is, the first sub-word lines WL1 _1, second sub-word lines WL1 ₂ and the bit lines BL, a first driving transistor QN1 is no connection between the inverted bit line * BL and the second driving transistor QN2 To the first sub-word line WL1 ₁
And the second sub-word line WL1 ₂ , bit line BL,
The connection to the inversion bit line * BL can be formed inside the first transfer transistor QW1 and the second transfer transistor QW2, and the circuit arrangement of the memory cell is simplified. Furthermore, the first driving transistor QN1 and the second driving transistor QN2 require a cross wiring to form a flip-flop circuit,
Although connected to the load L, these wirings and the position where the load L is formed are inside the first transfer transistor QW1 and the second transfer transistor QW2, and the circuit configuration of the memory cell MC itself is simplified. , Can be reduced, and the manufacturing process can be simplified. Nodes NA and NB
, That is, the position where the TFT transistor is formed is also a balanced position. The active area can be simplified, the LOCOS can be easily obtained, and the element isolation process can be easily performed. The bit contact pads 101 and 102 located around the inverted bit line * BL and the bit line BL contact portion can also be provided with sufficient margin.

FIG. 5 shows the connection state of the word lines WL according to the second embodiment of the present invention. FIG. 5 shows a memory cell M in the row (column) direction among the memory cells MC arranged in a matrix.
It is a partial view of C. These memory cells MC are driven by the word line WL1, but as described above,
Although a row decoder connected to the word line WL1 is branched into a first sub-word lines WL1 ₁ and the ₂ second sub-word line WL1 in memory cell portion, The first
Sub word lines WL1 ₁ and second sub-word line WL of
1 ₂ and is long there is a potential difference and the timing difference between them occurs. Therefore, a predetermined number of memory cells M
Each C, for example, 4 each memory cell MC, and the first sub-word lines WL1 ₁ and the second connection line CL1~CL2 which the sub-word line WL1 ₂ shorted connection is arranged, the occurrence of such a potential difference and timing difference Preventing.

As described above, an example in which a thin film TFT transistor is used for the load L as the memory cell MC has been described.
The present invention relates to E / R type SRAM, E / D type SRAM, CM
The same applies to OS-type SRAMs and the like.
For example, in an E / R type SRAM, a high resistance element may be formed instead of the thin film transistor (TFT) as the load L.

[0026]

As described above, according to the present invention, a conventional SRAM is provided by branching a word line from a row decoder into a pair of sub-word lines driven in phase in a memory cell portion. It is possible to solve various problems caused by the complexity of the arrangement caused in the device, to simplify the active region, to simplify the element isolation process, and to eliminate the unstable operation. Further, according to the present invention, design rules can be simplified and the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a matrix arrangement of memory cells and connection of word lines and bit lines to these memory cells as a first embodiment of the SRAM device of the present invention.

FIG. 2 is a diagram showing a circuit configuration of one memory cell in the SRAM device shown in FIG. 1 and a connection state of a word line and a bit line to the memory cell;

3 is a plan view showing a basic arrangement of elements constituting a memory cell of the SRAM device shown in FIG. 2, and word lines and bit lines BL.

FIG. 4 shows the SRAM device shown in FIG. 3;
3 is a more detailed plan view of the basic arrangement shown in FIG.

FIG. 5 is a diagram showing a matrix arrangement of memory cells and connection of word lines and bit lines to these memory cells as a second embodiment of the SRAM device of the present invention.

FIG. 6 is a circuit configuration diagram of one memory cell in a conventional SRAM device.

FIG. 7 is a plan view of a circuit of the memory cell shown in FIG. 6;

[Explanation of symbols]

MC ... memory cells, QW1, QW2 .. transfer transistor P QN1, QN2 ... driving transistor, WL ... wordline WL1 _1, WL1 ₂ ... sub word lines, 10 ... active region, 101 and 102 ..Pad for bit contact.

Claims (3)

(57) [Claims] An input terminal is connected to a positive polarity and a negative polarity (inverted) bit line, and a control terminal supplies first and second in-phase word selection signals branched from one word line. And first and second transfer transistors each having an output terminal connected to the first and second nodes, and a load terminal each connected to the first and second nodes. And a control terminal connected to the second and first nodes to form a first flip-flop circuit.
And a second driving transistor, and first and second loads connected to respective load terminals of the first and second driving transistors via the first and second nodes. The bit lines of the positive polarity and the negative polarity are arranged close to and parallel to each other, and the first and second sub-word lines are substantially orthogonal to the bit lines, and are formed on a layer different from the bit lines. The bit lines are disposed in parallel with an interval therebetween, and are located between the closely disposed positive and negative bit lines and substantially at the center of an internal region sandwiched between the first and second sub-word lines. A power supply contact portion for grounding of the first and second driving transistors is disposed on both sides of the power supply contact portion for grounding which is inclined by approximately 45 ° with respect to the bit line or the sub word line. The first bit line below the positive and negative bit lines.
And a second driving transistor are arranged. The first driving transistor, a first node and the first transfer transistor are arranged side by side along the positive polarity bit line, and the first driving transistor is arranged along the positive polarity bit line. The first transfer transistor is disposed below or near the sub-word line of the second word line, and the second driving transistor, the second node and the second transfer transistor are arranged along the negative bit line. The second transfer transistor is disposed below or near the second sub-word line, and the power supply contact portion for grounding is rotated near the first and second nodes. A static RAM device, wherein each of the first and second loads is disposed at a symmetric position. 2. The method according to claim 1, wherein the first and second driving transistors are MOS transistors, and the first and second transfer transistors are M transistors.
An OS transistor, wherein the first and second loads are TFTs, and a first polysilicon layer formed on a substrate comprises the first and second driving transistors and the first and second loads. A second polysilicon layer formed on the first polysilicon layer and a gate electrode of the second transfer transistor, and a second polysilicon layer formed on the first polysilicon layer. Wherein a third polysilicon layer formed on the second polysilicon layer comprises a gate electrode of the TFT, the first and second nodes, and the first and second driving transistors. 2. The transistor according to claim 1, wherein a wiring with the gate electrode is formed, and a fourth polysilicon layer formed on the third polysilicon layer forms a power wiring and an active layer of the TFT. Click RAM device. 3. The static RAM device according to claim 1, further comprising a connection line commonly connecting said first and second sub-word lines at predetermined intervals.