JPH0621395A - Semiconductor memory and its manufacture - Google Patents

Abstract

PURPOSE:To provide a multi-port RAM capable of reducing the layout area on a semiconductor integrated circuit. CONSTITUTION:High-resistance loads 7 and 8 are composed of a high resistance polysilicon layer, and memory nodes N1 and N2 in a memory cell 50 are connected to ports through the medium of wirings 9 and 10 by the polysilicon layer of the second layer and buried contacts 20, 21, 22, and 23. The channel types of all transistors 1, 2, 3, 4, 5, and 6 used are N-type, and their layout area on a semiconductor integrated circuit is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a multi-port RAM such as a 2-port static RAM formed on a semiconductor integrated circuit and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 1 is an overall circuit diagram of a 2-port static RAM, and FIG. 2 is a circuit diagram of a conventional memory cell shown in FIG. In this example, for example, "CMOS VL
Principles of SI Design "(Weste, Eshradian
(Eshraghian) Co-authored by Takashi Tomizawa, translated by Yasuo Matsuyama, published by Maruzen,
P.310). 1 and 2, the wiring is shown for one memory cell 50 out of a large number of memory cells arranged in an array.

In FIG. 1, reference numerals 51 and 52 are for decoding the input address information to obtain desired word lines WL1 and WL.
2 is an address decoder for driving 2. Reference numeral 53 is a write driver that drives and controls the write operation to the memory cell 50 based on the input data, and 54 is a sense amplifier that detects the data stored in the memory cell 50 and obtains the output data. The write driver 53 and the sense amplifier 54 have bit lines B1, B1 and bit lines B2, B2.
And are connected.

Further, in FIGS. 1 and 2, 1, 2, 3,
4, 5 and 6 are N-type transistors, and 11 and 12 are P-type transistors. The bit line B1 is connected to the source terminal of the N-type transistor 3, and the drain terminal of the N-type transistor 3 is connected through the storage node N1 to the gate terminals of the N-type transistor 1 and the P-type transistor 11 and the N-type transistors 2 and P.
The drain terminal of the type transistor 12 is connected.
Further, the bit line bar B1 is connected to the source terminal of the N-type transistor 4, and the drain terminal of the N-type transistor 4 is connected via the storage node N2 to the gate terminals of the N-type transistor 2 and the P-type transistor 12 and the N-type transistor 1. , And to the drain terminal of the P-type transistor 11. These bit lines B1 and B1 are a pair of bit lines for the first port used in a pair. N-type transistor 3,
A word line WL1 for the first port, which is used when reading and writing data using the bit line B1 and the bar B1, is connected to each gate terminal 4 of FIG.

A bit line B2 is connected to the source terminal of the N-type transistor 5, and the drain terminal of the N-type transistor 5 is connected through the storage node N1 to the gate terminals of the N-type transistor 1 and the P-type transistor 11 and the N-type transistor 2. , P
The drain terminal of the type transistor 12 is connected.
The bit line bar B2 is connected to the source terminal of the N-type transistor 6, and the drain terminal of the N-type transistor 6 is connected to the gate terminals of the N-type transistor 2 and the P-type transistor 12 and the N-type transistor 1 via the storage node N2. , And to the drain terminal of the P-type transistor 11. These bit lines B2 and B2 are a pair of bit lines for the second port used in a pair. N-type transistor 5,
A word line WL2 for the second port used when reading and writing data using the bit line B2 and the bar B2 is connected to each gate terminal of 6.

The source terminals of the N-type transistors 1 and 2 are grounded. The power source Vcc is connected to the source terminals of the P-type transistors 11 and 12. The potentials of the storage nodes N1 and N2 change according to the voltages of the bit line and the word line.

Next, the operation will be described. First, the first
A case of writing data from the port to the memory cell 50 will be described. The write driver 53 sets the data to be written in the memory cell 50 on the bit line B1 and sets the inverted signal of the data on the bit line bar B1. Next, the word line WL1 is driven to drive the N-type transistors 3 and 4
Turn on. For example, the bit line B1 has a high voltage "
In the "H" state, the voltage of the bit line bar B1 is low "
It is assumed that it is in the L state. When the word line WL1 is driven,
In the H state, the storage node N1 is in the "H" state and the storage node N2 is in the "L" state.After that, the word line WL1 is in the "L" state and the N-type transistors 3 and 4 are provided.
Even if is turned off, the potential at the storage node N1 is maintained in the "H" state and the potential at the storage node N2 is maintained in the "L" state, and is maintained as a stable state.

Next, the case of reading data from the first port will be described. First, the bit line B1 and the bar B1 are precharged. Next, the address decoder 51 drives the word line WL1 to turn on the N-type transistors 3 and 4. When the storage node N1 is in the "H" state and the storage node N2 is in the "L" state, the bit line B1 is maintained in the precharged state, and the bit line bar B1 is discharged to be in the "L" state. Then, the data stored in the storage nodes N1 and N2 are read out to the sense amplifier 54 via the bit line B1 and the bar B1.

Since the data write / read operation by the second port is the same as the data write / read operation by the first port, the description thereof will be omitted. However, in this case, the bit line B2 and the bar B2
And word line WL2 and N-type transistors 5 and 6 are used.

In the semiconductor memory device using the memory cell having the above-mentioned structure, a certain address selected by using the word line WL1 is accessed from the bit line B1 and the bar B1 and selected by using the word line WL2. Can be accessed from the bit line B2 and the bar B2. Such a 2-port memory cell is often used inside a recent microprocessor.

FIG. 3 shows a layout example when the 2-port memory cell of FIG. 2 is formed on a semiconductor integrated circuit, and FIG. 4 is a sectional view thereof. This layout is made up of one polysilicon layer 60 and two metal layers 61, 62.
The bit lines B1, B1, B2, B2 are formed by the second metal layer 62, and the wiring for supplying the power supply Vcc and the ground potential GND is formed by the first metal layer 61. There is.

[0012]

The conventional semiconductor memory device is configured as described above and includes a P-type transistor and an N-type transistor.
Type transistors coexist, so the distance between both transistors should be at least 5 μm in the 0.8 μm design rule.
It is necessary to provide the above, and there is a problem that there is a limit to miniaturization of the memory cell.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device which can reduce the layout area and realize the miniaturization of the entire device, and a manufacturing method thereof. To do.

[0014]

A semiconductor memory device according to the present invention has a plurality of polysilicon layers, a load element is formed of one polysilicon layer, and a storage node and a port are formed in a second layer. It is characterized in that it is configured to be connected through the above-mentioned one polysilicon layer and the buried contact.

In the method of manufacturing a semiconductor memory device according to the present invention, a plurality of polysilicon layers are formed, and a load element is formed by not implanting impurities into one polysilicon layer, and one load layer of the second or higher layer is formed. It is characterized in that the storage node and the port are connected by a polysilicon layer and a buried contact.

[0016]

According to the present invention, since the channel types of all the transistors used can be unified to N type (or P type), the semiconductor integrated circuit can be compared to the conventional example in which N type and P type transistors are mixed. The layout area on the circuit is reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments.

FIG. 5 is a circuit diagram of a characteristic portion of the 2-port static RAM according to the present invention. The overall circuit diagram is the same as that shown in FIG. 1, 2, 3, 4, in the figure
Reference numerals 5 and 6 are N-type transistors. N-type transistor 3
Is connected to the bit line B1 and the drain terminal of the N-type transistor 3 is connected to the gate terminal of the N-type transistor 1 via the buried contact 21 and the storage node N1.
It is connected to the drain terminal of the N-type transistor 2 and the high resistance load 7. The bit line bar B1 is connected to the source terminal of the N-type transistor 4, and the drain terminal of the N-type transistor 4 is connected to the gate terminal of the N-type transistor 2 and the N-type transistor 1 via the buried contact 22 and the storage node N2. Is connected to the drain terminal and the high resistance load 8. These bit lines B1 and B1 are a pair of bit lines for the first port used in a pair. Each of the gate terminals of the N-type transistors 3 and 4 has a bit line B1 and a bar B1.
The word line WL1 for the first port used when reading and writing data using is connected.

The bit line B2 is connected to the source terminal of the N-type transistor 5, and the drain terminal of the N-type transistor 5 includes a buried contact 20, a wiring 9 which is a medium resistance portion, a buried contact 21, and a storage node N1. It is connected to the gate terminal of the N-type transistor 1, the drain terminal of the N-type transistor 2, and the high resistance load 7 via the. The bit line bar B2 is connected to the source terminal of the N-type transistor 6,
The drain terminal of the N-type transistor 6 has a buried contact
It is connected to the gate terminal of the N-type transistor 2, the drain terminal of the N-type transistor 1 and the high resistance load 8 via 23, the wiring 10 which is a medium resistance portion, the buried contact 22, and the storage node N2. These bit lines B2 and bar B2
Are bit line pairs for the second port used in pairs. A word line WL2 for the second port used when reading and writing data using the bit line B2 and bar B2 is connected to each gate terminal of the N-type transistors 5 and 6. The source terminals of the N-type transistors 1 and 2 are grounded. A power supply Vcc is connected to the high resistance loads 7 and 8, respectively, and a voltage is supplied via the high resistance loads 7 and 8.

FIG. 6 shows a layout example when the circuit shown in FIG. 5 is formed on a semiconductor integrated circuit, and FIG. 7 is a sectional view thereof. N-type transistors 1, 2, 3, 4, 5,
Each gate terminal 6 is formed by the first polysilicon layer. The bit lines B1, bars B1, B2, B2 are formed of the first metal layer. High resistance load 7,8
Are formed by not implanting impurities into the second polysilicon layer. Wiring 9, 10 which is a medium resistance part
Is formed by implanting impurities into the second polysilicon layer. Also, embedded contacts 20, 21, 2
Reference numerals 2 and 23 are contacts which can directly connect the polysilicon layer and the diffusion region forming the source or drain of the transistor without the metal layer.

The bit line B2 is connected to the source terminal of the N-type transistor 5 by a normal diffusion contact. The drain terminal of the N-type transistor 5 is connected to the drain terminal of the N-type transistor 3 via the second polysilicon layer,
It is connected to the gate terminal of the N-type transistor 1 and the high resistance load 7. The drain terminal of the N-type transistor 5 and the second polysilicon layer are connected using the buried contact 20. The bit line bar B2 is connected to the source terminal of the N-type transistor 6 by a normal diffusion contact. N
The drain terminal of the N-type transistor 6 is connected to the drain terminal of the N-type transistor 4, the gate terminal of the N-type transistor 2 and the high resistance load 8 via the second polysilicon layer.
Connected to. The drain terminal of the N-type transistor 6 and the second polysilicon layer are connected using a buried contact 23. The voltage is supplied through the second polysilicon layer connected to the high resistance loads 7 and 8. The ground potential is connected to the diffusion region forming the source terminals of the N-type transistors 1 and 2. Each of the bit line B1 and the bit line bar B1 is connected to the source terminals of the N-type transistor 3 and the N-type transistor 4 by a normal diffusion contact.

Next, a method of manufacturing the semiconductor memory device having such a structure will be described with reference to FIGS.

First, P on the surface side of the P-type silicon substrate 31.
Well 32 and N well 33 are formed (FIG. 8A). Then P
A field insulating film 34 made of a SiO ₂ film is formed at the boundary between the well 32 and the N well 33 (FIG. 8B). P well 32
After forming a gate insulating film 35 made of a SiO ₂ film on the entire surface of the N well 33 (FIG. 8C), the gate insulating film 35 is formed.
First gate made of the first polysilicon layer in the center of the
36 is formed (FIG. 8 (d)). The P well 32 and the N well 33 below the gate insulating film 35 where the first gate 36 is not formed
In addition, for example, by ion implantation, the N ⁺ diffusion region 37, P ⁺
The diffusion regions 38 are respectively formed (FIG. 9E). Then S
After forming the iO ₂ film 39 over the entire area, one of the N ⁺ diffusion regions 37
To form a buried contact hole 40 (see FIG. 9).
(f)), a second gate 41 made of a second polysilicon layer is formed in the buried contact hole 40 (FIG. 9).
(g)). Next, after further forming the SiO ₂ film 42 over the entire area, a contact hole 43 reaching the other N ⁺ diffusion region 37 and P ⁺ diffusion region 38 is formed (FIG. 10 (h)), and the contact hole 43 is formed. A first Al layer 44, which is the first metal layer, is formed (FIG. 10 (i)). After further forming the SiO ₂ film 45 on the entire area, S
Through hole reaching part of the iO ₂ film 45 to the first Al layer 44
46 is formed, and the second Al layer 47 which is the second metal layer is formed in the through hole 46 (FIG. 10 (j)).

Next, the operation of the semiconductor memory device of the present invention will be described.

First, the case of writing data from the first port to the memory cell 50 will be described. Write driver 53
Thus, the data to be written in the memory cell 50 is set on the bit line B1 and the inverted signal of the data is set on the bit line bar B1. Next, the address decoder 51 drives the word line WL1 to turn on the N-type transistors 3 and 4. For example, it is assumed that the bit line B1 is in a high voltage "H" state and the bit line bar B1 is in a low voltage "L" state. When the word line WL1 is driven to be in the "H" state, the storage node N1 is in the "H" state and the storage node N2 is in the "L" state. Then word line WL1
Is set to the "L" state and the N-type transistors 3 and 4 are turned off, the potential at the storage node N1 is kept at the "H" state and the potential at the storage node N2 is kept at the "L" state, and the stable state is maintained. It is maintained and data is written.

Next, the case of reading data from the first port will be described. First, the bit lines B1 and B1 are precharged. Next, by the address decoder 51,
The word line WL1 is driven to turn on the N-type transistors 3 and 4. When the storage node N1 is in the "H" state and the storage node N2 is in the "L" state, the bit line B1 is maintained in the precharged state, and the bit line bar B1 is discharged to be in the "L" state. Then, the data stored in the storage nodes N1 and N2 is the bit line B.
1, read to the sense amplifier 54 via the bar B1.

Since the data writing / reading operation by the second port is similar to the data writing / reading operation by the first port, the description thereof will be omitted. However, in this case, the bit line B2, the bar B2, the word line WL2, and the N-type transistors 5 and 6 are used.

In the above-mentioned embodiment, the structure having two polysilicon layers is adopted. However, if necessary, the polysilicon layer may be composed of three or more layers, and one polysilicon of the second layer or more may be formed. The storage node and the port may be connected by a layer and a buried contact.

[0029]

As described above, in the semiconductor memory device of the present invention, the load element is formed of the high resistance polysilicon layer,
Since the storage node and the port in the memory cell are connected by one polysilicon layer of the second layer or more and the buried contact, the channel types of all the transistors used can be unified into one semiconductor. There is an effect that the layout area on the integrated circuit can be reduced (the layout area can be reduced to about half) compared to the conventional example. In a multi-port memory having a write-only port, when the present invention is applied to the write-only port, a particularly practical effect is achieved.

[Brief description of drawings]

FIG. 1 is an overall circuit diagram of a 2-port storage device.

FIG. 2 is a partial circuit diagram of a conventional semiconductor memory device.

FIG. 3 is a plan view showing a layout example of a conventional semiconductor memory device.

FIG. 4 is a sectional view showing a layout example of a conventional semiconductor memory device.

FIG. 5 is a partial circuit diagram of an embodiment of a semiconductor memory device of the present invention.

FIG. 6 is a plan view showing a layout example of an embodiment of the semiconductor memory device of the present invention.

FIG. 7 is a cross-sectional view showing a layout example of an embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a cross-sectional view showing a part of the manufacturing process of the embodiment of the semiconductor memory device of the present invention.

FIG. 9 is a cross-sectional view showing a part of the manufacturing process of the embodiment of the semiconductor memory device of the present invention.

FIG. 10 is a sectional view showing a part of the manufacturing process of the embodiment of the semiconductor memory device of the present invention.

[Explanation of symbols]

 7,8 High resistance load 9,10 Wiring by the second polysilicon layer 20, 21, 22, 23 Buried contact 50 Memory cell N1, N2 Storage node

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[Procedure amendment]

[Submission date] November 4, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

First, P on the surface side of the P-type silicon substrate 31.
Well 32 and N well 33 are formed (FIG. 8A). Then, theft
A field insulating film 34 made of a SiO ₂ film is formed in the region where the transistor is not formed (FIG. 8B). After the gate insulating film 35 made of a SiO ₂ film is formed on the entire surface of the P well 32 and the N well 33 (FIG. 8C), the first polysilicon layer is formed at the center of the gate insulating film 35. The first gate 36 is formed (FIG. 8 (d)). An N ⁺ diffusion region 37 and a P ⁺ diffusion region 38 are formed in the P well 32 and the N well 33 below the gate insulating film 35 where the first gate 36 is not formed, for example, by an ion implantation method (see FIG. 9 ( e)). Then SiO ₂
After the film 39 is formed over the entire area, a buried contact hole 40 reaching one of the N ⁺ diffusion regions 37 is formed (FIG. 9F), and the buried contact hole 40 is formed with a second polysilicon layer as a second layer. The gate 41 is formed (FIG. 9 (g)). 2nd game
Root 41, except for the areas that form the high resistance load,
Inject to form the second gate wiring with medium resistance
It Next, a SiO ₂ film 42 is further formed over the entire area, and then a contact hole 43 reaching the other N ⁺ diffusion region 37 and P ⁺ diffusion region 38 is formed (FIG. 10 (h)).
A first Al layer 44, which is the first metal layer, is formed on 43 (see FIG.
10 (i)). After further forming the SiO ₂ film 45 on the entire area,
_A through hole 46 reaching the first Al layer 44 is formed in a part of the _second film 45, and a second Al layer 47 which is a second metal layer is formed in the through hole 46 (FIG. 10 (j)).

Claims (2)

[Claims] 1. A semiconductor memory device having a plurality of ports and a storage node, comprising: a plurality of polysilicon layers; and a load element in which one of the polysilicon layers has a high resistance, A semiconductor memory device having a structure in which a node and a port are connected to each other through a second or more polysilicon layer of the polysilicon layer and a buried contact. 2. A method of manufacturing a semiconductor memory device by connecting a plurality of ports to a storage node, wherein a plurality of polysilicon layers are used, and one of the polysilicon layers is used.
A layer is made to have a high resistance to form a load element, and the storage node and the port are connected by a polysilicon layer of a second layer or more of the polysilicon layer and a buried contact. Method of manufacturing semiconductor memory device.