JPH10270573A - Positive logic element sram memory cell circuit and positive logic element latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory cell circuit having a small number of elements and a static random access memory(SRAM) at low manufacturing cost. SOLUTION: A latch circuit is constituted by connecting a gate electrode and a drain electrode using two positive logic circuits of P-type and N-type on which an input signal and an output signal become unipolarity, and the latch circuit is used as an SRAM latch circuit. The circuit surrounded by a broken line 15 functions as a latch circuit, the circuit surrounded by a broken line 16 functions as a transmission gate, and the circuit surrounded by a broken line 10 corresponds to the SRAM memory cell circuit of the positive logic element. As a result, the memory cell circuit of the SRAM is obtained by four transistors, the latch circuit is obtained by two transistors, and a low cost SRAM can be provided. also, a latch circuit having a small number of element can be formed in the general circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static random access memory (hereinafter referred to as SR) using a semiconductor integrated circuit.
AM), which relates to a circuit configuration of a memory cell which has a high degree of integration and element efficiency using a positive logic element and is suitable for high-speed operation.

[0002]

2. Description of the Related Art A conventional SRAM memory cell circuit is shown in FIG.
Insulated gate field effect transistor (hereinafter referred to as MO
(Abbreviated as SFET) Four latch circuits 915 and N-type (or P-type) MOSFETs from both ends thereof
In this configuration, the signal stored in the latch circuit via 913 and 914 and its inverted signal are taken out to two bit lines 919 and 920. Then, as shown in the overall arrangement and configuration of FIG.
9 and 920 are converted into differential comparator circuits 1001
To determine the signal stored in the memory cell.

[0003]

In the above-described conventional memory cell configuration, four MOS transistors are provided in one latch circuit.
FETs are used, and two MOSFETs are used as transmission gates. That all depends on the storage capacity. In the SRAM, which generally requires a large capacity year by year, the use of four MOSFETs in the latch circuit of one memory cell increases the manufacturing cost and increases the manufacturing cost. There is a problem that the cost is about four times as large as that of the dynamic RAM (DRAM).

Accordingly, an object of the present invention is to provide a memory cell circuit having a small number of elements and to provide an SRAM with a low manufacturing cost in order to solve or alleviate such problems.

[0005]

The positive logic element memory cell circuit of the present invention uses two P-type and N-type positive logic elements.
It is characterized by comprising a latch circuit formed by connecting all the drain electrodes and the first gate electrode to each other, and a transmission gate formed of a positive logic element or a MOSFET.

[0006]

According to the above configuration of the present invention, the latch circuit can be composed of P-type and N-type positive logic elements, so that only two elements are required for the latch circuit. Also, reading the signal of the latch circuit by the transmission gate,
Further, data can be written to the latch circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. First, it is an important key of the present invention. The positive logic element will be described first.

FIG. 3 is a sectional view of an element showing an embodiment of a positive logic element used in the present invention. In FIG. 3, reference numeral 31 denotes a first gate electrode connected to an input signal. Reference numerals 32 and 33 are made of a P-type diffusion layer and serve as a source electrode or a drain electrode. The source electrode is connected to a positive power supply directly or via another element. 34,
Reference numeral 35 denotes a second gate of a so-called floating gate which is not directly connected to a signal.
Formed on the channel 36 between the two 33
Reference numeral 5 denotes a portion that does not ride on the channel. Reference numerals 37 and 38 denote insulating layers mainly containing silicon dioxide. The channel 36 is made of a lightly doped N-type diffusion layer. When a positive potential is applied to the first gate 11, a negative charge is induced in the portion 34 above the channel of the second gate because it is immediately below the first gate. Since the second gate itself has zero electric charge as a whole, a portion 3 where the same amount of positive electric charge as the negative electric charge induced at 34 is not on the channel at the second gate.
5 induced. As a result, the portion 34 of the second gate on the channel is charged with a negative potential including the lower portion. Therefore, a positive charge is induced in the channel 36, and the source and drain electrodes 32 and 33 are turned on (conducting) with each other. FIG. 4 shows this state. As a result, a positive potential output is obtained for a positive potential input signal. When a negative potential is applied to the first gate 31, the + and-of the charges in FIG. 2 are all reversed, and the source and drain electrodes 32 and 33 are turned off (disconnected). This is shown in FIG. Therefore, it can be seen that the element of FIG. 3 is a positive logic element. Since a P-type diffusion layer is used, it will be referred to as a P-type positive logic element hereinafter.

In FIG. 3, a case has been described where 32 and 33 are P-type diffusion layers and 36 is a lightly doped N-type diffusion layer. However, 32 and 33 are N-type diffusion layers and 36 is a lightly doped P-type diffusion layer.
In the case of the type diffusion layer, when a negative potential is applied to the first gate electrode 11, the source and drain electrodes 32 and 33 are turned on (conducting) with each other, and the first gate electrode 3 is turned on.
When a positive potential is applied to 1, elements 32 and 33 are turned off (disconnected) with each other. Since an N-type diffusion layer is used, it will be referred to as an N-type positive logic element hereinafter.

FIG. 1 is a circuit diagram of a positive logic element SRAM memory cell showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 15 functions as a latch circuit, a circuit surrounded by a broken line 16 functions as a transmission gate, and a circuit surrounded by a broken line 10 corresponds to the positive logic of the present invention. It corresponds to an element SRAM memory cell circuit. Now, in the broken line 15, reference numeral 11 denotes a P-type positive logic element, and the source electrode is connected to V _DD which is a positive power supply.
The gate electrode and the drain electrode are connected to each other. Further, 12 is an N-type positive logic element, the source electrode is connected to V _SS a power supply of the positive electrode, the first gate electrode and the drain electrode are connected to each other. In addition, the drain electrode of the P-type positive logic element 11 and the drain electrode of the N-type positive logic element 12 are connected to each other to form an input / output terminal 17. The P-type positive logic element 11 is turned on (conducting) when the first gate electrode is at a positive potential, and the positive potential V _DD flows into the drain electrode and is fed back to the first gate electrode. Has a function to stably hold. The first
If the gate electrode has a negative potential, it is off (non-conductive).

The N-type positive logic element 12 is turned on (conducting) when the first gate electrode is at a negative potential, and the negative potential V _SS flows into the drain electrode and is fed back to the first gate electrode. Has a function of stably maintaining a negative potential. Note that when the first gate electrode has a positive potential, it is off (disconnected). Therefore, the circuit composed of the P-type positive logic element 11 and the N-type positive logic element 12 has a latch circuit 15 that stably holds either the positive potential (V _DD ) or the negative potential (V _SS ).
It turns out that it becomes. Reference numeral 13 denotes a P-type positive logic element. Two terminals serving as a source electrode or a drain electrode serve as a first terminal and a second terminal of the transmission gate 16, and the first gate electrode is connected to a word line 18. . Reference numeral 14 denotes an N-type MOSFET, and two terminals serving as a source electrode or a drain electrode are a first terminal and a second terminal of the transmission gate 16. The gate electrode is connected to the word line 18.

The second terminal of the transmission gate is connected to the data line 19, and the first terminal is connected to the input / output terminal 17 of the latch circuit 15. Both the P-type positive logic element 13 and the N-type MOSFET turn on when the word line 18 has a positive potential, and turn off when the word line 18 has a negative potential. 13 is a P type,
It can be seen that 14 is an N-type transmission gate that reliably transmits both positive and negative potentials. With the above configuration, when the word line becomes positive potential, data can be written from the data line 19 to the latch circuit 15, and the data held in the latch circuit 15 can be transferred to the data line 1.
6 can also be taken out. When the word line 18 is at a negative potential, the latch circuit 15 is disconnected from the data line 19 and holds data.

FIG. 2 shows the positive logic element SRAM described with reference to FIG.
How memory cells are used throughout SRAM
Are shown in a more understandable manner. Figure 2
The blocks indicated by the broken line 10 are all the memories described in FIG.
Cell. In FIG. 2, the first line from the top (actually the L-th line)
The Lth word line W _L
Input the transmission gate in each memory cell.
The first gate electrode of the P-type positive logic element and the N-type MO
Each gate electrode of the SFET is controlled. From above
Memory that is arranged side by side in the second row (actually the L-1 row)
The cell group includes the (L-1) th word line W_L-1Is entered,
Similarly, each memory cell is controlled. The first row from the left
(Actually, the M-th column)
M-th bit line B_MOf each transmission gate
It is connected to the second terminal. The second column from the left (actually M
(M--1)
1) The first bit line B_M-1Are each transmission game
Connected to the second terminal. 21 is write
Write controlled by composite signal WC of signal and column signal
22 is a combined signal of the read signal and the column signal.
This is a read circuit controlled by RC. Bit line
B_MIs the output terminal of the write circuit 21 and the read circuit 22
Is connected to the input terminal of Also, the writing circuit 21
The column read / write circuit 20 including the read circuit 22
It is provided for each bit line. Well, the data at (L, M)
When reading data, the Lth word line is activated.
And the read circuit 22 connected to the M-th bit line
Make it work. Also write the data at address (L, M)
When replacing, the L-th word line is activated and the M-th word line is activated.
Operating the write circuit 21 connected to the bit line
You. As described above, data at any address can be read.
It turns out that you can also write. The diagram of the present invention
1 and FIG. 2 are compared with FIG. 9 and FIG.
There are two transistors per memory cell,
It turns out that there is one less data line per row of memory cells
You. This is very unusual for an integrated circuit device as an SRAM.
Reduction of large components, cost reduction, or
Contributes to miniaturization.

FIG. 6 is a circuit diagram of a positive logic element SRAM memory cell showing a second embodiment of the present invention. In FIG. 6, a circuit surrounded by a broken line 15 functions as a latch circuit, a circuit surrounded by a broken line 66 functions as a transmission gate, and a circuit surrounded by a broken line 60 corresponds to the positive logic of the present invention. The element corresponds to an SRAM memory cell circuit. Here, the difference from the circuit of FIG. 1 is that the configuration in the transmission gate 66 and the inversion word line 68 having the relationship of the inversion signal of the word line 18 are added. In the circuit in the broken line 66 that is the transmission gate, the P-type positive logic element 13 and the N-type positive logic element 64 are used. Since the N-type positive logic element 64 is used, the inverted word line 68 having an inverted signal relationship with the signal on the word line 18 is connected to the first gate electrode of the N-type positive logic element. Otherwise, the configuration and function are the same as those of the circuit of FIG.

The circuit shown in FIG. 6 has the advantage that the number of inverting word lines is increased by one, but is unified with positive logic elements. FIG. 8 shows how the memory cell described in FIG. 6 is used in the entire SRAM. In FIG. 8, all the blocks indicated by broken lines 60 are the memory cells described in FIG. 1 line from the top in FIG. 8 (actually L-th row) in the memory cell group are arranged laterally to enter the IW _L of L th word line W _L and an inverted signal, in each memory cell Transmission gate N-type and P-type MOSF
The gate electrodes of the ET are respectively controlled. The (L-1) th word line WL _-1 and its inverted signal IWL _-1 are input to the memory cell group arranged horizontally in the second row (actually the L-1 row) from the top. Thus, each memory cell is similarly controlled. Further, an M-th bit line B _M is connected to the second terminal of each transmission gate in the memory cell group vertically arranged in the first column (actually, the M-th column) from the left. The (M-1) th bit line B _M-1 is connected to the second terminal of each transmission gate in the memory cell group vertically arranged in the second column (actually the M-1 column) from the left. ing.
Otherwise, it is the same as FIG. FIG. 8 is different from FIG. 2 in that a plurality of inverted word lines IW are added to the overall arrangement.

When an inverted word line as shown in FIG. 8 is required, the use efficiency of the area on a plane is improved by using two layers of aluminum wiring.

FIG. 7 is a circuit diagram of a positive logic element SRAM memory cell showing a third embodiment of the present invention. In FIG. 7, a circuit surrounded by a broken line 15 functions as a latch circuit, a circuit surrounded by a broken line 76 functions as a transmission gate, and a circuit surrounded by a broken line 70 corresponds to the positive logic of the present invention. The element corresponds to an SRAM memory cell circuit. Here, the difference from the circuit of FIG. 6 is that the configuration in the transmission gate 76 is a P-type MOSFET 74 and an N-type MOSFET.
That is, T73 was used. The overall configuration is the same as that of FIG. Since the circuit of FIG. 7 uses MOSFETs for all transmission gates, there is an advantage that the element density is slightly improved.

In the transmission gate of the circuit shown in FIG. 1, an N-type positive logic element and a P-type MOSFET
Can also be used. Although the above description has been made on the assumption that the present invention is applied to the SRAM, the latch circuit 15 used in FIGS. 1, 6, and 7 is naturally useful as a latch circuit in circuits other than the SRAM. is there.

[0019]

As described above, according to the positive logic element SRAM memory cell circuit of the present invention, since the latch circuit is composed of two positive logic elements, the conventional latch requiring four elements is required. There is an effect that an efficient SRAM memory cell circuit having a smaller number of elements than a circuit can be provided.

Therefore, there is an effect that an inexpensive SRAM can be provided.

Further, since the number of elements is small and a differential circuit is not used at the time of data reading, there is an effect that a memory cell with low current consumption and low power consumption and an SRAM can be provided.

Further, the positive logic element latch circuit of the present invention has an S
It can be used for devices other than the RAM, and has an effect that it can be configured with a small number of elements.

[Brief description of the drawings]

FIG. 1 shows a positive logic element SRA according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram of an M memory cell circuit.

FIG. 2 is a circuit diagram showing a relationship between a positive logic SRAM memory cell circuit of the first embodiment of the present invention and peripheral circuits in the SRAM circuit;

FIG. 3 is a sectional view showing a configuration of a positive logic element used in the positive logic element SRAM memory cell circuit of the present invention.

FIG. 4 is a charge distribution diagram showing the operation of the positive logic element used in the positive logic element SRAM memory cell circuit of the present invention.

FIG. 5 is a charge distribution diagram showing the operation of the positive logic element used in the positive logic element SRAM memory cell circuit of the present invention.

FIG. 6 shows a positive logic element SRA according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of an M memory cell circuit.

FIG. 7 shows a positive logic element SRA according to a third embodiment of the present invention.
FIG. 3 is a circuit diagram of an M memory cell circuit.

FIG. 8 is a circuit diagram showing a relationship between a positive logic SRAM memory cell circuit according to a second embodiment of the present invention and peripheral circuits in the SRAM circuit;

FIG. 9 is a circuit diagram of an SRAM memory cell circuit of a conventional circuit example.

FIG. 10 is a circuit diagram showing a relationship with peripheral circuits in a RAM circuit of a conventional circuit example.

[Description of Signs] 10, 60, 70... Positive logic element SRAM memory cell
Circuits 11, 13: P-type positive logic element 12, 64: N-type positive logic element 14, 73, 913, 914: N-type MOSFET 74: P-type MOSFET 15: Latch circuit 16 , 66, 76: transmission gate 17: input / output terminal  18, W_L, W_L-1, W_L-2, 918 ... word line  68, IW_L, IW_L-1, IW_L-2... Wave of inverted signal
Line 19, B_M, B_M-1, B_M-2, B_M-3, 919, 920 ...
-Bit line 20-Column read / write circuit 21-Write circuit 22-Read circuit 910-Memory cell circuit 1001-Differential sense amplifier circuit WC-Synthesis of write signal and column signal Signal RC: Composite signal of read signal and column signal VDD: Positive power supply potential VSS: Negative power supply potential

Claims (6)

[Claims] A) a first electrode and a second electrode which are formed of a diffusion layer and serve as a source electrode or a drain electrode; a first gate electrode to which an input signal is applied; and a floating gate which is not directly connected to a signal. A second gate electrode;
A gate electrode is located above a channel between the first electrode and the second electrode made of the diffusion layer, and a part of the second gate electrode of the floating gate is a part of the first electrode and the second electrode made of the diffusion layer. Between the channel between the first gate electrode and
A semiconductor integrated circuit device having a positive logic element having a structure located other than on the channel; and b) a first P-type positive logic element and a second N-type positive logic element. The source electrode of the P-type positive logic element is connected to the positive power supply, the second N-type positive logic element source electrode is connected to the negative power supply, and the first gate electrode of the first P-type positive logic element is connected to the drain. An electrode, and a first of a second N-type positive logic element.
A latch circuit in which the gate electrode and the drain electrode are all connected to each other to serve as an input terminal and an output terminal; and c) a third P-type positive logic element and an N-type insulated gate field-effect transistor. 3) a transmission gate comprising a positive logic element and a source electrode or a drain electrode of an N-type insulated gate field effect transistor connected to each other, and d) an input terminal and an output terminal of the latch circuit are connected to the transmission gate. A first terminal of the transmission gate is connected to a bit line as a memory, and a first terminal of the third P-type positive logic element and a gate electrode of the N-type insulated gate field effect transistor are connected to a second terminal. Are connected to a word line as a memory. Moriseru circuit. 2. The positive logic element SRA according to claim 1, wherein the transmission gate comprises a fourth N-type positive logic element and a P-type insulated gate field effect transistor.
M memory cell circuit. 3. a) a first electrode and a second electrode comprising a diffusion layer and serving as a source electrode or a drain electrode; a first gate electrode to which an input signal is applied; and a floating gate not directly connected to a signal. A second gate electrode;
A gate electrode is located above a channel between the first electrode and the second electrode made of the diffusion layer, and a part of the second gate electrode of the floating gate is a part of the first electrode and the second electrode made of the diffusion layer. Between the channel between the first gate electrode and
A semiconductor integrated circuit device having a positive logic element having a structure located other than on the channel; and b) a first P-type positive logic element and a second N-type positive logic element. The source electrode of the P-type positive logic element is connected to the positive power supply, the second N-type positive logic element source electrode is connected to the negative power supply, and the first gate electrode of the first P-type positive logic element is connected to the drain. An electrode, and a first of a second N-type positive logic element.
A latch circuit in which the gate electrode and the drain electrode are all connected to each other to form an input terminal and an output terminal; and c) a third P-type positive logic element and a fourth N-type positive logic element, A transmission gate formed by connecting a source electrode or a drain electrode of each of the third and fourth positive logic elements to each other; and d) an input / output terminal of the latch circuit is connected to a second terminal of the transmission gate. A first terminal of the transmission gate is connected to a bit line as a memory; a first gate electrode of the third P-type positive logic element is connected to a first word line as a memory; A first gate electrode of the element is connected to a second word line having an inverted signal relationship with the first word line; AM memory cell circuit. 4. A first electrode and a second electrode comprising a diffusion layer and serving as a source electrode or a drain electrode, a first gate electrode to which an input signal is applied, and a floating gate which is not directly connected to a signal. A second gate electrode;
A gate electrode is located above a channel between the first electrode and the second electrode made of the diffusion layer, and a part of the second gate electrode of the floating gate is a part of the first electrode and the second electrode made of the diffusion layer. Between the channel between the first gate electrode and
A semiconductor integrated circuit device having a positive logic element having a structure located other than on the channel; and b) a first P-type positive logic element and a second N-type positive logic element. The source electrode of the P-type positive logic element is connected to the positive power supply, the second N-type positive logic element source electrode is connected to the negative power supply, and the first gate electrode of the first P-type positive logic element is connected to the drain. An electrode, and a first of a second N-type positive logic element.
A latch circuit in which the gate electrode and the drain electrode are all connected to each other to serve as an input terminal and an output terminal; and c) an N-type insulated gate field effect transistor and a P-type insulated gate field effect transistor. Type and P
A) a transmission electrode in which a source electrode or a drain electrode of an insulated-gate field-effect transistor is connected to each other; and d) an input / output terminal of the latch circuit is connected to a second terminal of the transmission gate. A first terminal of the transmission gate is connected to a bit line as a memory; a gate electrode of the N-type insulated gate field effect transistor is connected to a first word line as a memory; A positive logic element SRAM memory cell circuit, wherein a gate electrode of the type transistor is connected to a second word line having an inverted signal relationship with the first word line. 5. The first and second embodiments according to claim 3 and 4.
Wherein the word lines are metal wirings of different layers in a semiconductor integrated circuit device using two or more layers of metal wirings. 6. a) a first electrode and a second electrode comprising a diffusion layer and serving as a source electrode or a drain electrode, a first gate electrode to which an input signal is applied, and a floating gate which is not directly connected to a signal. A second gate electrode;
A gate electrode is located above a channel between the first electrode and the second electrode made of the diffusion layer, and a part of the second gate electrode of the floating gate is a part of the first electrode and the second electrode made of the diffusion layer. Between the channel between the first gate electrode and
A semiconductor integrated circuit device having a positive logic element having a structure located other than on the channel; and b) a first P-type positive logic element and a second N-type positive logic element. The source electrode of the P-type positive logic element is connected to the positive power supply, the second N-type positive logic element source electrode is connected to the negative power supply, and the first gate electrode of the first P-type positive logic element is connected to the drain. An electrode, and a first of a second N-type positive logic element.
A positive logic element latch circuit in which the gate electrode and the drain electrode are all connected to each other to serve as an input terminal and an output terminal.