JPH1187533A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a SRAM memory cell the writing time of which is not restricted and, furthermore, area of which is small. SOLUTION: In SRAM memory cells MC1 and MC2 which are respectively composed of four transistors, thin film MOS transistors are employed as access transistors Q13, Q14, Q23 and Q24 and pairs of the drive transistors (Q11 and Q12) and (Q21 and Q22) are formed in different wells, respectively. Voltages (BG or BG') applied to the respective well regions, which include the transistors on the continuity side among the pairs of the transistors, are higher than the voltage (BG' or BG) applied to the respective well regions which include the transistors on a non-continuity side among the pairs of the transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a memory cell of a static random access memory (hereinafter, referred to as "SRAM").

[0002]

2. Description of the Related Art In recent years, the degree of integration of SRAMs has increased, and the area occupied by each memory cell must be reduced. As shown in FIG. 3, four bulk transistors Q1 to Q4,
Since the occupied area of the six-element memory cell MC1 composed of the two load elements L1 and L2 is determined by the minimum dimensions of the bulk transistors Q1 to Q4, it has been determined by the fine processing technology. In the figure, N1 and N2 are storage nodes, WL1 is a word line, DATA and DATAB.
Is a data line pair.

However, at present, since the fine processing technology has not been able to sufficiently meet the demand for high integration, the area occupied by the memory cell array is increasing with the increase in density. As a result, the size of the semiconductor chip constituting the SRAM becomes large, and the manufacturing yield decreases,
There is a problem that the size of the package is increased.

On the other hand, two drive transistors of a memory cell are constituted by bulk transistors, two access transistors are constituted by thin film transistors, and a data line pair is connected to a power supply voltage via a load element. Thereby, as compared with the above-described six-element memory cell including the four bulk transistors Q1 to Q4 and the two load elements L1 and L2, the memory cell can be configured three-dimensionally, and the semiconductor occupied by each memory cell can be configured. S that provides the effect of reducing the area on the substrate
A RAM memory cell has been proposed (Japanese Patent Laid-Open No. 5-62).
474, JP-A-6-104405).

FIG. 2 is a circuit diagram of the SRAM. In the figure, Q11, Q12, Q21 and Q22 are memory cells M
C1 and MC2 are drive transistors, which are formed as bulk transistors on a semiconductor substrate. Q13, Q14, Q23, and Q24 are access transistors, and are formed as thin film transistors (TFTs) above the bulk transistors. I have. Q
5, Q6 are load elements for supplying current to the data lines DATA, DATAB, and WL1 and WL2 are word lines. The data bit is stored as a potential difference between the storage nodes N11 and N12 or between N21 and N22, and input data is supplied as a potential difference between the data line pair DATA-DATAB (Vcc [power supply potential] -GND [ground potential]. ], Or GND-Vcc).

When word lines WL1 and WL2 are at low level,
When the memory cells MC1 and MC2 are not selected, the data line pair DATA and DATAB are at the power supply potential by the load elements Q5 and Q6. In addition, the memory cells MC1 and M
One of the storage nodes N11, N12, N21, N22 in C2 is at a high level, and the other is at a low level. The storage nodes holding the high level in the memory cells MC1 and MC2 tend to decrease in voltage due to the leak current, but the sub-threshold leak currents of the access transistors Q13, Q14, Q23, Q24 have the data lines whose power supply potentials Supplied to maintain a high level from DATA and DATAB, and maintain a high level.

At present, the ratio of the on-state internal resistance to the off-state internal resistance of an N-type bulk transistor having a channel length of 1 to 0.8 μm and a channel width of 2 to 3 μm is 1: 1 × 10
It will be about ⁹ . The leakage current of the storage nodes N11 and N12 of the memory cell in which the bulk transistor is configured as a drive transistor is about several pA. On the other hand, the ratio of the on-state internal resistance to the off-state internal resistance of the current thin film transistor is about 1: 1 × 10 ⁶ . Therefore, access transistors Q13, Q
If thin-film transistors are used for Q14, Q23 and Q24 and the current capability in the on state is set to about 100 to 150 μA, the sub-threshold leakage current in the off state becomes 100 to 150 pA, and the storage node N1
1, the storage node N11 or N12 can be maintained at a high level by exceeding the leakage current of N12.

[0008]

The SRA shown in FIG.
M cell is the data line pair DA selected during the write operation.
Consider a case where the memory cell is a non-selected memory cell connected to TA and DATAB. That is, in FIG. 2, the data lines DATA and DATAB are selected (DATA: Vc
c, DATAB: GND), consider a non-selected memory cell MC2 when the memory cell MC1 is a selected memory cell and the memory cell MC2 is a non-selected memory cell.

As described above, when the data line DATAB goes low, the high level of the storage node N22 changes to the level of the access transistor Q24 constituted by a thin film transistor.
Level starts to decrease due to the sub-threshold leak. At this time, the access transistor Q24 is off because the word line WL2 is at a low level, and the access transistor Q14 is on because the word line WL1 is at a high level.

Since the resistance ratio of the thin-film transistor in the on / off state is 1: 1 × 10 ⁶ , as described above, the period T1 in which the data line DATAB is at a low level corresponds to a period in which the storage node N12 is changed from a high level to a low level. By setting the transition time to the minimum necessary time, the high-level storage node N22 of the non-selected memory cell MC2 is hardly affected by the transition of the data line DATAB to the low level, and the data "
However, it is difficult to optimally set the period T1 due to the variation in the on-resistance or the off-resistance of the access transistors Q14 and Q24. Considering this, if you set a sufficient time for data writing,
Unselected memory cells may be corrupted, while
If you try to prevent data corruption in unselected memory cells,
There is a problem that a sufficient writing time cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional SRAM memory cell, and has as its object to provide an SRAM memory cell having no restriction on the write time.

[0012]

A semiconductor memory device according to the present invention comprises a plurality of memory cells formed on a substrate, and a plurality of word lines and data lines connected to the plurality of memory cells. A semiconductor memory device comprising: a pair of drive transistors each including a transistor formed on the substrate; and a memory cell including a pair of access transistors including a thin film transistor formed above the substrate. In the semiconductor memory device, the pair of drive transistors of the memory cell are respectively formed in different regions on the substrate.

In the semiconductor memory device according to the present invention, when data is written to the memory cell, the data is applied to a region where one of the pair of drive transistors that is turned on is formed. Voltage
The voltage is higher than a voltage applied to a region where the other transistor to be turned off is formed.

Further, in the semiconductor memory device of the present invention, at the time of writing data to the memory cell, one of the pair of drive transistors is connected to one of the drive transistors which is turned on. A node applies an intermediate voltage (an intermediate voltage between the power supply potential Vcc and the ground potential GND) lower than that of the other data line to one of the data line pairs coupled via the access transistor. .

The cause of data corruption in the unselected memory cells is that one of the data lines is changed to the ground potential at the time of data writing. In view of this point, in the present invention, as a method of writing data, a pair of drive transistors constituting a memory cell are respectively formed in separate well regions on a semiconductor substrate, and a side to be brought into a conductive state is formed. The potential of the well in which the drive transistor is formed is made higher than the potential of the well in which the other drive transistor is formed, so that the drive transistor is changed to a conductive state and data is written. Adopted. Thereby, basically, data writing can be performed while the potentials of the data line pair are both at the power supply potential, and data corruption of non-selected memory cells due to a subthreshold leak of the access transistor is prevented. Therefore, it is possible to set a sufficient writing time without any restrictions.

Further, at the time of data writing, the potential applied to the data line on the side of the drive transistor which is turned on is set to an intermediate potential between the power supply potential Vcc and the ground potential GND.
For example, by adopting a configuration in which the power supply potential is set to Ｖ Vcc (the other data line is supplied with the power supply potential Vcc), the state transition speed of each drive transistor in the selected memory cell can be increased. Thus, the data write time can be shortened. However, as the level of the intermediate potential approaches the ground potential, the data write time in the selected memory cell is shortened, and the possibility of data corruption in the non-selected memory cell is increased. It is necessary to set the level of the intermediate potential.

As a result, S with no restriction on the writing time
A memory cell of a RAM can be provided.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an SRA according to an embodiment of the present invention.
It is a circuit diagram of M.

In the figure, Q11, Q12, Q21, Q22
Are drive transistors that constitute the memory cells MC1 and MC2, are configured as bulk transistors on a semiconductor substrate, and are Q13, Q14, Q23, and Q2.
Reference numeral 4 denotes an access transistor, which is configured as a thin film transistor (TFT) above the bulk transistor. Here, drive transistors Q11 and Q11
21 are both formed in the first well region,
Drive transistors Q12 and Q22 are both formed separately from the first well (independent from each other).
Is formed in the well region. Q5 and Q6 are load elements for supplying current to the data lines DATA and DATAB, and WL1 and WL2 are word lines. The data bit is stored as a potential difference between the storage node pair N11 and N12 or between the storage node pair N21 and N22.

FIG. 4 is a plan pattern diagram of the SRAM circuit shown in FIG.

Referring to FIG. 4, in a memory cell MC1, two P-type wells 2 and 3 are formed inside an N-type semiconductor substrate 1. Bias voltages BG and BG ′ are separately applied to the respective P-type wells. The P-type wells 2 and 3 have a source,
N-type diffusion layers 4 and 5 are provided as drain regions. On the semiconductor substrate 1, a gate oxide film is provided. On the gate oxide film, N channel MOS transistors Q11, Q1 are formed by a first polysilicon layer.
Two gates 6 and 7 are formed. An insulating layer is provided on the first polysilicon layer, and second polysilicon layers 8 and 9 are provided on the insulating layer. One end of this second polysilicon layer is
And 12 are connected to the diffusion layers 4 and 5 via first polysilicon layers 6 and 7, respectively. Further, an insulating layer is provided on the second polysilicon layers 8 and 9, and a third polysilicon layer 10 is provided on the insulating layer. By this third polysilicon layer 10, N-channel thin film MOS transistors Q13 and Q1 are formed.
The word line WL1 serving as the gate of No. 4 is formed. An insulating layer is provided on the third polysilicon layer 10,
Data lines DATA and DATAB made of aluminum wiring are provided on the insulating layer. The data lines DATA and DATAB are respectively connected to the contact portions 13
And 14, the second polysilicon layers 8 and 9
To the other end. The second polysilicon layer 8
In the portion facing the gate 6, an N-channel thin film MO
A channel region of S transistor Q13 is formed, and an N-type diffusion region serving as a source / drain is formed on both sides of the channel region. That is, the channel region and the source / drain region of the N-channel thin film MOS transistor Q13 are formed in the second polysilicon layer 8. Similarly, the second polysilicon layer 9 has an N-channel thin film MO
A channel region and a source / drain region of S transistor Q14 are formed.

In the memory cell MC2, two P-type wells 2 and 3 are formed inside an N-type semiconductor substrate 1. As described above, the bias voltages BG and BG ′ are separately applied to the respective P-type wells. The P-type wells 2 and 3 have a source,
N-type diffusion layers 24 and 25 are provided as drain regions. On the semiconductor substrate 1, a gate oxide film is provided. On the gate oxide film, an N-channel MOS transistor Q21 is formed by a first polysilicon layer.
Gates 26 and 27 of Q22 are formed. This first
An insulating layer is provided on the polysilicon layer, and second polysilicon layers 28 and 29 are provided on the insulating layer. One end of the second polysilicon layer is connected to the diffusion layers 24 and 25 via first polysilicon layers 26 and 27 at contact portions 31 and 32, respectively. Further, the second polysilicon layers 28 and 2
An insulating layer is provided on 9, and a third polysilicon layer 20 is provided on this insulating layer. The word line W serving as the gates of the N-channel thin film MOS transistors Q23 and Q24 is formed by the third polysilicon layer 20.
L2 is formed. An insulating layer is provided on the third polysilicon layer 20, and data lines DATA and DATAB made of aluminum wiring are provided on the insulating layer. The data lines DATA and DATAB are connected to the second
Are connected to the other ends of the polysilicon layers 28 and 29.
In the second polysilicon layer 28, an N-channel thin-film MOS transistor Q2
Three channel regions are formed, and an N-type diffusion region serving as a source / drain is formed on both sides of the channel region. That is, the channel region and the source / drain region of the N-channel thin film MOS transistor Q23 are formed in the second polysilicon layer 28. Similarly, the channel region and the source / drain region of the N-channel thin film MOS transistor Q24 are formed in the second polysilicon layer 29.

FIGS. 5 and 6 are cross-sectional views taken along the line AA 'and cross-section taken along the line BB' in FIG. 4, respectively.

The P-type wells 2 and 3 shown in FIG.
The memory cell may be common to all memory cells in the column direction (vertical direction), may be common to a plurality of memory cells in units of banks or blocks in the column direction, or may be divided into P-wells for each cell. Is also good. The point is that one and the other of the pair of drive transistors of each memory cell need only be formed in different well regions.

Next, the operation of the SRAM of this embodiment will be described in detail.

First, consider a state in which the memory nodes N11 and N21 of the memory cells MC1 and MC2 hold a low level and the storage nodes N12 and N22 hold a high level.

In the standby state, the data lines DATA, DAT
Since AB is at the Vcc level and the word lines WL1 and WL2 are at the low level, the resistance of the access transistor is sufficiently large and the drive transistors Q11 and Q2 in the ON state
1 is sufficiently larger than the ON resistance of the drive transistors Q11 and N21.
12 and Q22, which are sufficiently lower than the threshold voltage Vt.
Drive transistors Q12 and Q22 maintain the off state, and the off-resistance of drive transistors Q12 and Q22 is sufficiently larger than the off-resistance of access transistors Q14 and Q24, so that the potentials of storage nodes N12 and N22 are set to drive transistors Q11 and Q22, respectively. Q
Drive transistors Q11 and Q21 maintain the ON state because they are sufficiently higher than threshold voltage Vt of V21.

When data is read from memory cell MC1, data lines DATA and DATAB are precharged to Vcc potential. Next, when the word line WL1 goes high, the access transistors Q13 and Q14 conduct, and a current flows through the path between the access transistor Q13 and the drive transistor Q11. Drive transistor Q12 is non-conductive, so that no current flows through the path between access transistor Q14 and drive transistor Q12. By detecting this current difference,
Data can be read.

When data "1" is written to the memory cell MC1, that is, when a high level is written to the storage node N11, when the data lines DATA and DATAB have the potential of Vcc and the word line WL1 has a high level, the access transistor Although the resistances of Q13 and Q14 decrease, the on-resistance of drive transistor Q11 is sufficiently smaller, and the potential of storage node N11 is sufficiently lower than threshold voltage Vt of drive transistor Q12, so that drive transistor Q12 is turned off. And the off resistance of drive transistor Q12 is
14 is sufficiently larger than the on-resistance of storage node N12.
Is sufficiently higher than the threshold voltage Vt of drive transistor Q11.
1 maintains the ON state.

Here, when the well potential BG 'of drive transistor Q12 rises above well potential BG of drive transistor Q11 and threshold voltage Vt of drive transistor Q12 falls sufficiently, storage node N1
The potential of 1 becomes higher than the threshold voltage Vt of drive transistor Q12, and drive transistor Q12 shifts to the ON state. When the ON resistance of drive transistor Q12 becomes sufficiently smaller than the ON resistance of access transistor Q14, the potential of storage node N12 becomes lower than threshold voltage Vt of drive transistor Q11, and drive transistor Q11 shifts to the off state. Thereby, the storage node N11 is at a high level and the storage node N12 is
Becomes low level, and data "1" is written.

In the above-mentioned writing method, the potentials of the data lines DATA and DATAB are both set to Vcc, but the intermediate potential Vm (GND <Vm) is applied to the data line DATAB.
<Vcc), the potential of the storage node N12 further decreases, and the drive transistor Q
Since the shift of the switch 11 to the off state can be performed more quickly, the writing time can be shortened.

Since the memory cell MC2 when data "1" is written to the memory cell MC1 is not selected, if the potentials of the data lines DATA and DATAB are Vcc and the word line WL2 is at a low level, the access transistor Q
23 and Q24 are sufficiently large and sufficiently larger than the ON resistance of the drive transistor Q21 in the ON state.
The potential of storage node N21 is equal to drive transistor Q2
2, the drive transistor Q22 maintains the off state, and the off resistance of the drive transistor Q22 is sufficiently higher than the off resistance of the access transistor Q24, so that the potential of the storage node N22 becomes lower than the drive transistor Q21. Drive transistor Q21 is kept on.

Here, even if the well potential BG 'of drive transistor Q22 rises above well potential BG of drive transistor Q21 and threshold voltage Vt of drive transistor Q22 drops, access transistor Q13 of memory cell MC1 does not lose the potential. Since the off-resistance of access transistor Q23 is sufficiently higher than the on-resistance, the potential of storage node N21 does not become higher than storage node N11, and drive transistor Q22 maintains the off state. Since the off resistance of drive transistor Q22 is sufficiently larger than the off resistance of access transistor Q24, the potential of storage node N22 is
21 becomes higher than the threshold voltage Vt, and the drive transistor Q21 maintains the ON state.

In this case, the potential of the data line DATAB is V
Even if it falls below cc, the off resistance of drive transistor Q22 is sufficiently larger than the off resistance of access transistor Q24, so the potential of storage node N22 is higher than threshold voltage Vt of drive transistor Q21, and drive transistor Q21 is turned on. To maintain.

The well is formed by a shallow junction process or an SOI (Silicon On Insulator) which can separate a body region corresponding to a well region of a bulk transistor for each transistor.
When formed by a process, the junction capacitance with the substrate is reduced, and the well (body) potential is easily changed in a short time.

[0037]

As described above in detail, according to the semiconductor memory device of the present invention, the voltage applied to the region including the transistor to be made conductive among the pair of drive transistors is changed to the non-conductive state. Data is written to the memory cell by setting the voltage higher than the voltage applied to the region including the transistor on the side to be set, so that the optimum write time can be set without considering data corruption of the unselected memory cell. Thus, it is possible to provide an extremely useful semiconductor memory device having no restriction on the writing time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of an SRAM which is a premise of the present invention.

FIG. 3 is a circuit diagram of a conventional general SRAM.

FIG. 4 is a plan pattern diagram of the embodiment shown in FIG. 1;

FIG. 5 is a cross-sectional view taken along the line A-A 'in FIG.

FIG. 6 is a cross-sectional view taken along the line B-B ′.

[Explanation of symbols]

MC1, MC2 Memory cell Q11, Q12, Q21, Q22 Drive transistor Q13, Q14, Q23, Q24 Access transistor N11, N12, N21, N22 Storage node WL1, WL2 Word line DATA, DATAB Data line 1 N-type semiconductor substrate 2, 3 P-type well BG, BG 'well potential

Claims (3)

[Claims] 1. A semiconductor memory device comprising: a plurality of memory cells formed on a substrate; and a plurality of word lines and data line pairs connected to the plurality of memory cells. A memory cell comprising a pair of drive transistors formed of transistors formed above and a pair of access transistors formed of thin film transistors formed above the substrate, wherein the pair of drive transistors of the memory cells is , Each being formed in another area on the substrate. 2. When writing data to the memory cell, a voltage applied to a region where one of the pair of drive transistors to be made conductive is formed by the other transistor to be made non-conductive. 2. The semiconductor memory device according to claim 1, wherein the voltage is higher than a voltage applied to a region to be formed. 3. A data line in which one storage node connected to one of the pair of drive transistors that is turned on when writing data to the memory cell is coupled via the access transistor. 3. The semiconductor memory device according to claim 2, wherein an intermediate voltage lower than that of the other data line is applied to one of the pair.