FR2793341A1 - STATIC MEMORY WITH FOUR UNBALANCED TRANSISTORS AT THE LEVEL OF THEIR LEAKAGE CURRENT AND METHOD FOR CONTROLLING SUCH A MEMORY - Google Patents

Abstract

The binary data written in the memory cell is maintained by applying a substrate effect to each storage transistor (TM3, TM4) so as to obtain a leakage current from each access transistor (TA1, TA2) at least ten times greater at the leakage current of each storage transistor.

Description

Static memory with four transistors unbalanced in terms of their

  Leakage current and method for controlling such a memory The invention relates to static random access memory cells (ceUllules SRAM: "Static Random access memory", in English), and in particular the control of such cells in their state

  static, that is to say their state of retention of the memorized data.

  The invention relates more particularly to such memory cells in which the access transistors are also used as a resistor in the retention state, which avoids the use of

additional resistive components.

  Such a cell is described in the article by NODA et al., Entitled "a 1.9 gm2 Loadless CMOS four-transistor SRAM cell in a

  0.18 gm logic technology ", IEEE 1998.

  In order to ensure correct retention of the data stored in such a cell, the authors of this article recommend that the leakage current of the storage transistors be significantly lower than the leakage current of the access transistors, typically in a ratio of

around 100.

  Such a relationship is obtained by technologically modifying the characteristics of the storage transistors compared to the transistors conventionally used in the same technology and within

other components.

  More specifically, the cell storage transistors have, when they are NMOS transistors (N-channel insulated gate field effect transistor), a higher threshold voltage VT which is for example obtained by a method well known to those skilled in the art, known as the "double VT process". This process, which is characterized by specific implantations, requires the use of additional masks in order not to disturb the simultaneous manufacture of the other NMOS transistors

  present on the integrated circuit which incorporates the cells of the memory plane.

  Access transistors, on the other hand, do not undergo any modification compared to conventional transistors in the same technology, and are in particular identical to other PMOS transistors.

  manufactured on the same integrated circuit.

  The invention aims to remedy this technological drawback and proposes a radically different solution to obtain acceptable retention of the data stored in a static memory cell at

four transistors.

  The invention therefore provides a method for controlling a static memory cell with four transistors having a static state in which the binary data written in the memory cell is maintained by causing a leakage current to flow in each access transistor.

  greater than the leakage current of each storage transistor.

  According to a general characteristic of the invention, the binary data written is maintained by applying a substrate effect to each storage transistor so as to obtain a leakage current from each access transistor at least ten times greater than the leakage current from

each storage transistor.

  It was first observed that a ratio of ten between the leakage current flowing in each access transistor and the leakage current of each storage transistor, constituted in the static state of the memory, a minimum acceptable condition for get retention

correct written data.

  Furthermore, in the prior art, this ratio was obtained by reducing the leakage currents of the storage transistors by an action of the technological type, that is to say by a modification of the

  technological characteristics of the storage transistors.

  The invention obtains this ratio by also reducing the leakage currents of the storage transistors, but not by an action of the technological type, but by an application of a substrate effect on each storage transistor, that is to say by applying different predetermined bias voltages to the substrate and the source of these transistors. Thus, according to the invention, the storage transistors remain transistors analogous to other transistors of the same technology usable in other components integrated within the

  integrated circuit which contains the cells of the memory plane.

  In other words, the invention does not require here

  modification of the manufacturing process of transistors of such a cell-

  static memory, compared to the conventional manufacturing process of

CMOS transistors.

  In a first variant of the invention, applicable to a memory cell in which the storage transistors are the N-channel transistors, the substrate of each storage transistor is polarized with a predetermined substrate voltage lower than the voltage of

  source of the storage transistor.

  Depending on the technological implementation used (single or triple well; "single-well" or "triple-well" in English), the substrate of each storage transistor is connected to ground and a pasitive voltage is applied to the source of the transistor (simple box) or we connect the source of each storage transistor to ground and we

  applies a negative substrate voltage (triple box).

  In a variant of the invention, applicable to a cell-

  memory whose storage transistors are P-channel transistors, the substrate of each storage transistor is biased with a predetermined substrate voltage greater than the source voltage of the

storage transistor.

  The higher the ratio between the leakage current of an access transistor and the leakage current of a storage transistor, the better the retention capacity of the written binary data. However, the higher this ratio, the greater the current consumption of the cell in the static state. Also, it was considered preferable not to exceed a ratio of 100 between the leakage current of an access transistor and the

  leakage current of a storage transistor.

  Furthermore, the higher the ratio, the greater the reduction in the dynamic range between a high logic level and a low logic level, which leads to cells that are slower to read and more sensitive to noise, or even a risk of inversion. of the written data, during

reading.

  For all these reasons, it was currently considered preferable to choose a voltage difference between the substrate and the source of the order of

  a few tenths of a volt to about 1 volt.

  The invention also relates to a memory device

  static comprising at least one memory cell with four transistors.

  According to a general characteristic of the invention, this device also comprises control means capable of applying a substrate effect on each storage transistor so as to obtain a leakage current from each access transistor at least ten times greater than the current of each memory transistor, and thus maintain

  the binary data written in the memory cell.

  According to an embodiment of the invention, in which the storage transistors are N-channel transistors, the control means are capable of biasing the substrate of each storage transistor with a predetermined substrate voltage lower than the

  source voltage of the storage transistor.

  When the substrate of each storage transistor and the general substrate of the integrated circuit incorporating said device (simple box technology), the control means are advantageously able to connect the substrate of each storage transistor to ground and to apply a positive voltage to source

of the transistor.

  On the other hand, when each storage transistor is produced in a P-type semiconductor well, isolated from the general substrate of the integrated circuit incorporating said device by a silicon area N (triple well technology), the control means can connect the source of each storage transistor to ground and apply a

negative substrate voltage.

  In an embodiment in which the storage transistors are P-channel transistors, the control means are capable of biasing the substrate of each storage transistor with a predetermined substrate voltage greater than the source voltage of the

memory transistor.

  Other advantages and characteristics of the invention

  will appear on examination of the detailed description of embodiments

  and of implementation, in no way limitative, and of the appended drawings, in which: - Figures 1 and 2 schematically illustrate a first variant embodiment and implementation of the invention; - Figures 3 and 4 schematically illustrate a second alternative embodiment and implementation of the invention; and - Figure 5 schematically illustrates a third variant of

  realization and implementation of the invention.

  In FIG. 1, the reference CM designates a static memory cell with four transistors, or memory point with four transistors, forming part of a memory plane produced within an integrated circuit and formed of several cells of the same type connected together so

known to those skilled in the art.

  More precisely, the memory cell CM comprises two access transistors TA1 and TA2, which in this case are PMOS transistors whose respective sources S1 and S2 are connected conventionally and respectively to the two bit lines ("bit lines" in English language)

of a column of the memory plan.

  The gates G1 and G2 of the two access transistors are connected together in a conventional manner and known to those skilled in the art, to an activation line or word line ("word lines" in English) allowing

  to select all the cells of the same memory plane line.

  The substrates ("bulk" in English) B1 and B2 of

  PMOS transistors are connected to their source S1, S2.

  Conventionally, the selection of a column and a line of the memory map makes it possible to select a particular memory cell

  for example to write or read binary data 0 or 1 there.

  The memory cell CM also includes two transistors

  TM3 and TM4 memory, which in this case are NMOS transistors.

  These NMOS transistors are mounted crossed. More precisely, the gate G3 of the transistor TM3 is connected to the drain D2 of the access transistor TA2, while

  that the gate G4 of the transistor TM4 is connected to the drain D 1 of the transistor TA 1.

  Furthermore, the drain D3 of the transistor TM3 is connected to the drain D 1 of the transistor TA1 and the drain D4 of the transistor TM4 is connected to the drain D2 of the

TA2 transistor.

  The substrates B3 and B4 of the transistors TM3 and TM4 are connected to ground and the sources S3 and S4 of these transistors are also connected to ground via a PMOS transistor referenced TCM, the gate of which is relive to the source. and which is therefore always passing. Writing and reading in such a memory cell are conventional operations and well known to those skilled in the art. As an indication, it is recalled here that, for a write operation for example in a cell, the memory cell is selected using the word line and applied, depending on the value 0 or 1 of the binary data to be memorized, either a zero voltage on the bit line of the column considered (source S2, for example) and the supply voltage Vdd on the other bit line (source S 1 in this case), or the opposite, i.e. a zero voltage on the source S 1 and the supply voltage Vdd on the source

S2.

  Thus, according to the value of the binary data to be memorized, we will obtain at drain D1 a voltage substantially equal to the voltage

  supply and to the drain D2 a zero voltage, or the reverse.

  It is now assumed, by way of example, that in the writing phase, a zero voltage has been applied to the source S2 and the supply voltage Vdd to the source S1. There is therefore at node D 1 a voltage slightly lower than Vdd and at node D2 a voltage substantially zero. In order to keep the stored binary data, the memory cell is then placed in a so-called "static" or retention state, in which, in accordance with FIG. 1, the access transistors TA1 and TA2 are blocked by applying to the times on their source and their grid the supply voltage Vdd. The storage transistor TM4 is in turn on, while the storage transistor TM3 is in turn

blocked.

  The access transistors then play the role in this static state.

  resistance and a retention condition of the memorized data, (i.e.

  i.e. in the example described, the condition for the voltage at Dl1 to remain high) is to obtain a leakage current from the access transistor TA 1 (which is blocked) much greater than the leakage current from the transistor

  TM3 memorization which is also blocked.

  In other words, in the present case, the retention condition is expressed in these terms "the drain-source current, that is to say in this case the leakage current Ioff of the PMOS transistor blocked with a voltage difference drain-source is substantially zero, must be at least ten times greater than the leakage current Ioff of the NMOS transistor which is blocked with a difference

  of drain-source voltage substantially equal to the voltage Vdd. "

  In the cell of figure 1, this condition is realized in

  applying a substrate effect to the NMOS TM3 and TM4 transistors, i.e.

  say by polarizing the sources of these transistors with a voltage

  higher than the substrate voltage which is in this case the mass.

  In the present case, the control means which make it possible to polarize the source with a voltage greater than that of the substrate, comprise the PMOS transistor TCM which is always on. So the

  source voltage is equal to the threshold voltage of the PMOS transistor that is

  ie in this case about 0.5 volts.

  Due to this substrate effect, the threshold voltage of the storage transistors is increased and therefore the leakage current lofft of these transistors is reduced (i.e. the drain-source current in the state

transistor blocked).

  A person skilled in the art therefore notices that this increase in the threshold voltage of the storage transistors, that is to say this reduction in the leakage current, was obtained not by a particular technological modification of the storage transistors forming the cells. -memory, compared to other NMOS transistors of the same wafer and used for other components, but keeping the same manufacturing process for all NMOS transistors made on this same wafer, and by polarizing sources and sources differently substrates

  NMOS transistors of static memory cells.

  A voltage difference between the source and the substrate of the order of 0.5 volts allows in the present case, to obtain, for a 0.25ptm technology, a ratio greater than 10, but not too large, between the current leakage of the access transistor and the leakage current of the transistor

  memorization while keeping an acceptable dynamic for the cell-

  memory. A ratio greater than 100 would lead to too high current consumption of the cell in the static state. Indeed, in this state the transistor TM4 is on. Those skilled in the art will be able to adjust the value of the substrate effect in order to obtain, in each application considered, an acceptable compromise between good retention of the data.

  stored, cell dynamics and current consumption.

  The polarization of the substrate and of the source of the storage transistors, which has just been described, is compatible with a

  so-called simple box technology, as illustrated in Figure 2.

  More precisely, in this figure, the reference SUB denotes the general semiconductor substrate of the semiconductor wafer within which the memory plane according to the invention is produced, but also possibly other components. This general SUB substrate is of the P type. Conventionally, within the SUB substrate, an N box is produced

  acting as substrate B for the PMOS transistor of the cell-

  memory. The drain and source areas are obtained by P + implantations while the PB substrate contact is made by

an N + establishment.

  An NMOS storage transistor is, in turn, produced directly by implantation in the substrate SUB. The source and drain regions are produced by N + type implantation, while the taking of

  PB eSt substrate produced by a P + box.

  In the variant embodiment illustrated in FIG. 3, the substrate effect is applied to the storage transistors TM3 and TM4 by this time connecting their source to ground and by applying to the substrates B3 and] 34 a predetermined voltage VR negative, for example of

in the order of- 1 volt.

  The control means REG which make it possible in the static state to apply this voltage VR may for example comprise a negative charge pump of conventional structure and well known from

the chrome of the business.

  This being the case, this solution is not applicable with the so-called simple box technology illustrated in FIG. 2, because the polarization of the substrate of the NMOS transistors with a negative voltage would amount to polarizing the entire substrate of the wafer with a negative voltage which can not be suitable for other NMOS transistors made within

  of this brochure and relating to other components.

  On the other hand, the solution of FIG. 3 is possible in a so-called triple box embodiment as illustrated in FIG. 4 and well known

of the skilled person.

  More precisely, while the PMOS transistors are produced in a manner analogous to that which has been described with reference to FIG. 2, the NMOS transistors are this time produced in another well P isolated laterally from the SUB substrate by a well N and vertically isolated from the substrate SUB by a layer of N-doped insulating silicon surmounting another layer of silicon N. Thus, it is easily possible to apply a negative substrate voltage on the contact socket PB of the NMOS transistor without for this polarize in the same way the general substrate of the

SUB brochure.

  It is also possible (FIG. 5) that a memory cell CM is formed of two NMOS access transistors and two PMOS type storage transistors. In this case, the retention condition is expressed as follows:

  "the leakage current of the access transistor with a drain-

  source close to 0, must be at least ten times greater than the leakage current of the storage transistor (PMOS type) with a voltage

  drain-source is equal to the supply voltage Vdd. "

  In this variant illustrated in FIG. 5, the substrates of the access transistors TAI and TA2 are connected to their source. The sources of the storage transistors TM3 and TM4 are connected to the supply voltage Vdd and, in the static state, the sources of the access transistors SI and S2 are connected to ground and the substrates B3 and B4 of the storage transistors are polarized by a predetermined voltage VR generated by means REG, comprising for example a charge pump capable of producing this voltage VR equal for example to Vdd + 1 volt_

  The invention thus makes it possible to very simply obtain a plan-

  memory of memory cells with four transistors, having acceptable retention conditions, and without modifying the methods for producing the transistors of this memory plane, compared to the other transistors of the

  integrated circuit which incorporates this memory plane.

  In addition, the additional cost brought by the realization of the REG means

  which can be carried out next to the memory plan, is minimal.

l

Claims (10)

  1. Method for controlling a static memory cell with four transistors having a static state in which the binary data written in the memory cell is maintained by circulating in each access transistor a leakage current greater than the leakage current of each storage transistor, characterized in that the binary data written is maintained by applying a substrate effect on each storage transistor (TM3, TM4) so as to obtain a leakage current from each access transistor (TA 1 , TA2) at least ten times higher   at the leakage current of each storage transistor.   2. Method according to claim 1, characterized in that the memory transistors (TM3, TM4) being N channel transistors, the substrate of each storage transistor is biased with a predetermined substrate voltage lower than the source voltage of storage transistor.   3. Method according to claim 2, characterized in that the substrate of each storage transistor (TM3, TM4) is connected to the   ground and a positive voltage is applied to the source of the transistor.   4. Method according to claim 2, characterized in that the source of each storage transistor (TM3, TM4) is connected to the   ground and a negative substrate voltage is applied.   5. Method according to claim 1, characterized in that the transistors de.mémorisation (TM3, TM4) being P channel transistors, the substrate of each storage transistor is biased with a predefined substrate voltage greater than the voltage of transistor source memorization.   6. Static memory device, comprising at least one memory cell with four transistors, characterized in that it further comprises control means (REG, TCM) capable of applying a substrate effect on each storage transistor (TM3, TM4 ) so as to obtain a leakage coBrant of each access transistor (TA1, TA2) at least ten times greater than the leakage current of each transistor   memorization, and thus maintain the binary data written in the cell- memory. -   7. Device according to claim 6, characterized in that the storage transistors being N-channel transistors, the control means (REG, TCM) are capable of biasing the substrate of each storage transistor with a predetermined substrate voltage lower than the source voltage of the storage transistor. 8. Device according to claim 7, characterized in that the substrate of each storage transistor is the general substrate of the integrated circuit incorporating said device, and in that the control means (TCM) are able to connect the substrate of each storage transistor to ground and apply a positive voltage to the source of the transistor.   9. Device according to claim 7, characterized in that each storage transistor is produced in a P-type semiconductor box isolated from the general substrate of the integrated circuit incorporating said device by an area of silicon N, and by the fact that the means control (REG) are able to connect the source of each storage transistor to ground and apply a voltage of negative substrate (VR).   10. Device according to claim 6, characterized in that the storage transistors being P channel transistors, the control means (REG) are capable of biasing the substrate of each storage transistor with a predetermined substrate voltage ( VR)   higher than the source voltage of the storage transistor.