JPH0660667A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To automatically initialize stored data immediately after turning on the power of SRAM in order to extend application by forming a flip-flop circuit with two inverters in different operation characteristics in a SRAM. CONSTITUTION:If the resistance of a resistance element R1 > the resistance of a resistance element R2, a voltage rises faster than storage nodes DN1, DN2 when the power switch is turned on. Thereby, a driving transistor (Tr) T1 turns on and the transistor T2 also turns on. Thereby, the node DL1 becomes L level, node DL2 becomes H level and the stored data '1' is initialized. Moreover, on the contrary, when R1 < R2, the stored data '0' is initialized. As explained above, by using a SRAM having an array of SRAM, the stored data can be initialized automatically as desired after the power is turned on, making unnecessary the initialization for writing the desired data in all the SRAMs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static random access memory (SR).
AM) memory cell structure.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an SRAM memory cell.

This SRAM cell comprises two inverters 1.
A flip-flop circuit 10 in which input and output nodes 1 and 12 are cross-connected, and between a pair of storage nodes (DN1, DN2) and a pair of bit lines (BL, / BL) of the flip-flop circuit 10, respectively. It is composed of a pair of transfer gate transistors 13 and 14 connected to each other, and each gate of the pair of transfer gate transistors 13 and 14 is connected to a word line WL.

As the inverters 11 and 12, an E / R type inverter composed of an enhancement type MOS transistor for driving and a high resistance element for load, or a CMOS inverter composed of complementary MOS transistors is used. FIG. 6 is a circuit diagram showing an E / R type flip-flop circuit using two E / R type inverters.
Here, T is a driving NMOS transistor, R is a load resistor, DN1 is a first storage node, and DN2 is a second storage node. FIG. 7 is a plan view showing an example of the pattern configuration of an SRAM cell using the E / R flip-flop circuit of FIG.

Reference numeral 71 denotes an impurity diffusion layer in the surface layer of the semiconductor substrate, which forms regions such as the drain region, the source region, and the source wiring (ground potential VSS) of the MOS transistor. Reference numeral 72 denotes a first layer polysilicon wiring, which forms the gate electrode of the MOS transistor.
Reference numeral 73 denotes a second layer polysilicon wiring, which forms a high resistance element, a power supply wiring (power supply potential VDD), and the like. 7
Reference numeral 4 is a contact region.

In the conventional SRAM cell, the two E / R inverters are designed to have the same load resistance size, transistor size, and parasitic capacitance so that the same operation characteristics can be obtained. There is.

By the way, in the conventional SRAM, the data storage content of the SRAM cell is indefinite when the power is turned on. Therefore, when the storage data is initially set when the SRAM is used, it is necessary to write desired storage data in all the SRAM cells, so that the use of the SRAM is greatly limited.

[0008]

As described above, the conventional SRAM requires an operation of writing desired storage data in all SRAM cells when initializing the storage data at the time of use. There was a problem of being limited.

The present invention has been made to solve the above-mentioned problems, and it becomes possible to automatically initialize the storage data of the SRAM immediately after the power is turned on as desired. The purpose of the present invention is to provide a semiconductor memory device that can be accessed normally and can be used for a wide range of applications.

[0010]

According to the present invention, in a semiconductor memory device having an array of SRAM cells, at least a part of the SRAM cells in a cell array uses a flip-flop circuit composed of two inverters having different operation characteristics. It is characterized by being.

[0011]

In manufacturing the SRAM, the stored data immediately after the power is turned on is "1" as the operating characteristic of the two inverters in the SRAM cell which is the target of the stored data initialization.
Alternatively, by manufacturing differently so as to be “0”, the stored data of the SRAM cell immediately after power-on can be automatically initialized as desired.

In this case, the operating characteristics of the two inverters are set to be different from each other by minimizing the operating characteristics within a range that can be initially set, so that after the initial setting is completed (after the power is turned on).
Can be accessed as usual, and can operate as a normal SRAM.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an SRAM according to an embodiment of the present invention.
2 shows an example of the pattern configuration of the SRAM cell in FIG.

In this SRAM, the SRAM cells arranged in a matrix form, as shown in FIG. 5, a flip-flop circuit in which the input and output nodes of two inverters are cross-connected, and a pair of the flip-flop circuits. It is composed of a pair of transfer gate transistors each connected between a storage node and a pair of bit lines, each gate being connected to a word line.

In the SRAM cell pattern shown in FIG. 1, D1 and S1 are the drain and source regions of the first NMOS transistor for driving, and D2 and S2.
Are drain and source regions of the second NMOS transistor for driving. D3 and S3 are the drain and source regions of the third NMOS transistor for the transfer gate, and D4 and S4 are the fourth N for the transfer gate.
The drain region and the source region of the MOS transistor. Each of these regions is formed of an impurity diffusion layer in the surface layer of the semiconductor substrate, and the source regions S1 and S2 are formed so as to be continuous with the source line (ground potential Vss) 1 formed of a diffusion layer.

Correspondingly, G1 and G2 are gate electrodes of the first driving transistor and the second driving transistor, and G3 is a gate electrode of the pair of transfer gate transistors, which are in the first layer. It consists of polysilicon wiring.

The gate electrode G1 of the first driving transistor is connected to the drain region D2 of the second driving transistor via the contact region CT2 and the diffusion layer wiring 2.

The gate electrode G2 of the second driving transistor is connected to the drain region D1 of the first driving transistor through the contact region CT1, the second layer polysilicon wiring 3 and the contact region CT5. There is. R1 and R2 are a first resistance element and a second resistance element for a load, and 4 is a power supply wiring (power supply potential VCC), and these are composed of a second-layer polysilicon wiring.

One end of the first resistance element R1 is connected to the power supply wiring 4, and the other end is connected to the contact region CT1 (first storage node DN1). One end of the second resistance element R2 is connected to the power supply wiring 4, and the other end is connected to the contact region CT2 (second storage node DN2).

The drain region D3 of the transfer gate transistor is connected to the first storage node DN1, and the source region S3 thereof is connected to one bit line BL (not shown) via the contact region CT3. ing.
In addition, the drain region D of the transfer gate transistor
4 is connected to the second storage node DN2, and its source region S4 is connected to the other bit line / BL (not shown) via the contact region CT4.

In the SRAM of the above embodiment, at least a part (all in this example) of memory cells in the memory cell array uses a flip-flop circuit composed of two inverters having different operation characteristics.

In order to make the operating characteristics of the two inverters different, in the present embodiment, the resistance value of the first resistance element R1 is larger than the resistance value of the second resistance element R2 (R1>
R2) so that two driving transistors T are formed.
1 and T2 are formed with the same size.

As a specific configuration example for realizing the above R1> R2, the pattern length a of the second resistance element R2 is the same as that of the first resistance element R1, but the second resistance element R2 is used. The pattern width b of is larger than that of the first resistance element R1.

In order to form in this way, the pattern width of the second resistance element R2 is shown by A in FIG. 1 when manufacturing the glass mask used in the step of forming the second layer polysilicon wiring. This can be realized by using pattern data (program data) that is created to be thicker than the pattern width of the first resistance element R1 by the area. Figure 2
FIG. 2 is a circuit diagram showing an E / R type flip-flop circuit in the SRAM cell of FIG. Where T1, T
Reference numeral 2 is a driving NMOS transistor, R1 and R2 are load resistors, DN1 is a first storage node, and DN2 is a second storage node. FIG. 3 is a characteristic diagram showing an operation in which stored data is initialized immediately after the power of the SRAM cell of FIG. 1 is turned on.

That is, since R1> R2, the potential of the second storage node DN2 rises faster than that of the first storage node DN1 when the power is turned on, the first drive transistor T1 is turned on, and the second drive transistor T1 is turned on. The transistor T2 is turned off. As a result, the first storage node DN1 becomes "L".
As a result, the level of the second storage node DN2 becomes "H" level, and the storage data "1" is initialized. In contrast to the above example, if the data is formed such that R1 <R2, the storage data “0” will be initialized.

According to the SRAM having the array of SRAM cells as described above, it is possible to automatically initialize the stored data immediately after the power is turned on as desired, so that the desired stored data can be stored in all the SRAM cells. The initial setting operation for writing is unnecessary.

In addition, the operating characteristics of the two inverters are made to be different to each other by suppressing the operating characteristics to the minimum within the range in which the initial setting is possible.
It becomes possible to access as usual, and it becomes possible to operate as a normal SRAM. Therefore, the SRAM of the above embodiment is
Corresponding to the read-only mask ROM, it can be referred to as a read / write mask RAM. As a modified example for making the operating characteristics of the two inverters different, the driving capabilities of the two driving transistors may be made different. FIG. 4 shows another example of the pattern configuration of the SRAM cell in the present invention.

In this example, the first driving transistor T
The first driving capacity gm1 is formed to be larger than the driving capacity gm2 of the second driving transistor T2, and the two resistance elements R1 and R2 are formed to have the same size. In FIG. 4, the same parts as those in FIG. 1 are designated by the same reference numerals.

In order to form the glass as described above, the first step is performed in manufacturing the glass mask used in the step of forming the diffusion layer.
4 can be realized by using the pattern data (program data) such that the channel width W1 of the driving transistor is made thicker than the channel width W2 of the second driving transistor by the area indicated by B in FIG.

Since the SRAM cell of FIG. 4 has gm1> gm2, the stored data "1" is initialized when the power is turned on. Contrary to the above example, if the data is formed so that gm1 <gm2, the storage data “0” will be initialized.

Furthermore, as another modified example for making the operating characteristics of the two inverters different, gate capacitors having different values are formed in the first storage node DN1 and the second storage node DN2, and two inverters are formed. Resistance elements R1 and R
2 having the same size and two driving transistors T
1 and T2 may be formed with the same size.

Although the above embodiment shows the SRAM integrated circuit, the present invention is not limited to this, and can be generally applied to a semiconductor integrated circuit in which the SRAM is mounted on the same chip as other circuits. Is.

[0033]

As described above, according to the present invention, the SRA
Since the stored data immediately after the power of M is turned on can be automatically initialized as desired, for example, by initializing the initial program and the initial constant, the operation of loading the initial program and the initial constant immediately after the power is turned on. Is unnecessary. Moreover, after the initial settings are completed (after power is turned on)
Can be accessed normally, and SRAM
The applications of can be expanded.

[Brief description of drawings]

FIG. 1 is a diagram showing an SR in an SRAM according to an embodiment of the present invention.
The top view which shows an example of the pattern structure of an AM cell.

FIG. 2 is a circuit diagram showing an E / R flip-flop circuit in the SRAM cell of FIG.

3 is a characteristic diagram showing an operation in which stored data is initialized immediately after power-on of the SRAM cell of FIG.

FIG. 4 is a plan view showing another example of the pattern configuration of the SRAM cell in the present invention.

FIG. 5 is a circuit diagram showing a general configuration of an SRAM cell.

FIG. 6 is a circuit diagram showing an E / R type flip-flop circuit in a conventional SRAM cell.

FIG. 7 is a plan view showing a pattern configuration corresponding to the SRAM cell of FIG.

[Explanation of symbols]

T1, T2 ... Driving transistor, R1, R2 ... Load resistance, D1 ... Drain region of driving transistor T1, S
1 ... Drain region of driving transistor T1, D2 ... Drain region of driving transistor T2, S2 ... Drain region of driving transistor T2, 1 ... Source wiring, 2 ...
Diffusion layer wiring, 3 ... Second layer polysilicon wiring, 4 ... Power supply wiring, DN1, DN2 ... Storage node.

Claims (1)

[Claims] 1. A flip-flop circuit in which input / output nodes of two inverters are cross-connected, and a flip-flop circuit is connected between a pair of storage nodes and a pair of bit lines, respectively, and each gate is a word. The memory cell array includes a pair of transfer gate transistors connected to the line, and at least a part of the memory cells in the memory cell array has a flip-flop circuit including two inverters having different operation characteristics. A semiconductor memory device characterized by being used.