JPH05315569A - Memory cell and semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a memory element and a semiconductor memory circuit device where initial data are determined. CONSTITUTION:A first inverter circuit is composed of a P-channel transistor 6b and an N-channel transistor 7b, and a second inverter circuit is composed of P-channel transistors 6a and 6d and an N-channel transistor 7a. The drain connection of the first inverter circuit is connected to the source of a third N-channel transistor 7c, and the drain of the transistor 7c is connected to a first bit line BIT. The drain connection of the second inverter circuit is connected to the source of a fourth N-channel transistor 7d, and the drain of the transistor 7d is connected to a second reverse bit line #BIT. The N-channel transistors 7c and 7d are connected to a word line WL with a gate common connection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell having a read / write memory function of a CMOS gate array and a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional semiconductor memory device having a read / write memory function using a basic cell constituting a CMOS gate array will be described below.

FIG. 1 is a schematic plan view of a conventional semiconductor integrated circuit device having a CMOS gate array. In the figure, reference numeral 1 is a semiconductor chip, and basic cell rows 3, 3 ... Are formed in the center of the semiconductor chip 1, and input / output pads 2, 2 ... Are formed in the peripheral portion of the semiconductor chip. FIG. 2 is an enlarged plan view of one row of the basic cell rows 3, 3 ... Shown in FIG. P-type diffusion region
4a and the N-type diffusion region 4b are arranged in parallel with their longitudinal directions parallel to each other. The gates 5a, 5a of the P-channel transistor are formed at equal intervals on the P-type diffusion region 4a, and the gates 5b, 5b of the N-channel transistor are formed on the N-type diffusion region 4b.
Are formed at equal intervals. Thereby, the P-type diffusion region
4a serves as the source and drain of the P-channel transistor, and the N-type diffusion region 4b serves as the source and drain of the N-channel transistor.
The channel transistors are arranged in two rows.

FIG. 3 shows the basic cell array 3 shown in FIG.
2 is an equivalent circuit diagram of FIG. P-channel transistor 6 and N
The channel transistors 7 are formed in series, respectively.
In such a basic cell row 3, an arbitrary transistor is OF
Since a transistor formed in series can be divided at that position by switching to the F state, a gate separation method can be used, so that a desired circuit can be formed by turning off a specific transistor.

FIG. 4 is a conceptual diagram when a semiconductor memory device is constructed on such a CMOS gate array. Basic cell rows 3, 3 ... Formed on the semiconductor chip 1
The semiconductor memory device 8 is formed in any area. Input / output pads 2 and 2 are provided around the semiconductor chip 1.
... is formed.

FIG. 5 is a block diagram of the semiconductor memory device 8 shown in FIG. Memory cells 9, 9 ... Are arranged side by side in a matrix, and an X decoder (word line decoder) 1 is provided near the memory cells.
0, write and read circuit 11, and Y decoder 12
Are formed. The semiconductor memory device 8 is an X decoder
The memory cell 9 selected by 10 and the Y decoder 12 is configured to perform a write operation and a read operation by the write and read circuit 11.

FIG. 6 is a circuit diagram of an arbitrary memory cell 9 among the memory cells 9, 9 ... Shown in FIG. In the figure, 6a and 6b are P-channel transistors, and 7a, 7b, 7c and 7d are N-channel transistors.

A P-channel transistor 6a is connected to the power supply line VDD.
Is connected to the P channel transistor 6a, and the N channel transistor 7a is connected in series to the P channel transistor 6a with a common gate and drain. The source of the N-channel transistor 7a is connected to the ground line GRD and constitutes a first inverter circuit. In addition, P to the power supply line VDD
The source of the channel transistor 6b is connected, and similarly, N
The channel transistors 7b are connected in series to form a second inverter circuit. The first and second inverter circuits are connected in parallel, and the drain section and the gate section of the first inverter circuit are connected to the gate section and the drain section of the second inverter circuit, respectively. The input part of such an inverter circuit is the respective gate connection part, and the output part is the respective drain connection part.
The first and second inverter circuits have their output parts connected to other input parts, and form a data holding loop.

The drain connection of the second inverter circuit is connected to the source of the N-channel transistor 7c, and its drain is connected to the bit line BIT. Also, the first
The drain connection part of the inverter circuit is connected to the source of the N-channel transistor 7d, and its drain is connected to the inverted bit line #BIT. The common connection portion of the gates of the N-channel transistor 7c and the N-channel transistor 7d is connected to the word line WL.

FIG. 7 is a layout diagram of the memory cell circuit shown in FIG. .. and 5b, ... Of the basic cell row 3 formed as shown in FIG. 2 are P-channel transistors 6a, 6b, 6c, 6d and N-channel transistors 7a, 7b ,. 7c and 7d are configured. The power supply line VDD, the ground line GRD, the bit line BIT and the inverted bit line #BIT are formed by the first layer wiring 13, and the word line WL is formed by the second layer wiring. The contact hole 15 connects the first layer wiring 13 to the source and drain (not shown) of the transistor, and also connects the first layer wiring 13 to the gate of the transistor. Then, the first layer wiring 13 and the second layer wiring are formed by the through holes 16.
14 and is connected.

As described above, FIGS. 7A and 7B both realize the memory cell circuit shown in FIG. 6, and any of them can be used to form a semiconductor memory device. Normally, by connecting Figure 7 (a) and Figure 7 (b) alternately,
It constitutes a semiconductor memory device. FIG. 8 is a layout diagram showing a state in which these memory cells are alternately connected. Word lines WL (n-1), WL (n), WL (n + 1) indicate word lines of adjacent memory cells, respectively. The same parts as those in FIGS. 7 (a) and 7 (b) are designated by the same reference numerals and the description thereof will be omitted.

The memory cell circuit configured as described above performs a data holding operation by the data holding loop composed of the first inverter circuit and the second inverter circuit. Further, by setting the word line WL to the “H” level, the respective output levels are read out to the bit line BIT and the inverted bit line #BIT through the transistors 7c and 7d. Further, by setting the inverse logic level to the bit line BIT and the inverted bit line #BIT by the write / read circuit 11 (shown in FIG. 5) and changing the word line WL from the “L” level to the “H” level, Write the set data. A conventional semiconductor memory device configured by such a memory cell circuit has a read / write memory function of performing a data holding operation, a reading operation, and a writing operation.

[0013]

In the memory cell circuit having such a configuration, since the first inverter circuit and the second inverter circuit have the same transistors connected in the same manner, a characteristic difference occurs between the respective inverter circuits. Absent. Therefore, it is not decided which inverter circuit outputs the "L" level first when the power is turned on, and when the first inverter circuit outputs the "L" level and when the "H" level is output.
There was a case to output the level. Therefore, in the conventional semiconductor memory device having the read / write memory function, the initial data output when the power is turned on is not fixed,
There was a problem that desired data had to be set every time the power was turned on.

The present invention has been made in view of such circumstances, and by making the characteristics of the first and second inverter circuits in the memory cell different, the initial data of the memory cell is determined when the power is turned on. It is an object of the present invention to provide such a memory cell and a semiconductor memory device.

[0015]

A memory cell according to the present invention includes a first inverter circuit and a second inverter circuit, and in a memory cell configured to be writable and readable, one P-channel transistor and one One N-channel transistor is connected in series to form a first inverter circuit, and two P-channel transistors and one N-channel transistor connected in parallel are connected in series to form a second inverter circuit. It is characterized by

A semiconductor memory device according to the present invention comprises a first inverter circuit and a second inverter circuit,
In a semiconductor memory device configured to be writable and readable by the second bit line and the second bit line, the data of the first inverter circuit is used for the first bit line, and the data of the second inverter circuit is used for the second bit. A first memory cell configured to output to a line, and data of the first inverter circuit to a second bit line, and data of a second inverter to a first bit line. And at least one of the second memory cell and the second memory cell.

[0017]

In the memory cell of the present invention, the circuit characteristics of the first inverter and the second inverter are made different, so that the respective logic voltage thresholds are different. When the power is turned on, the inverter circuit with the lower logic voltage threshold must always be "L" first.
Since the level is output, the inverter circuit having the higher logic voltage threshold always outputs the “H” level, and the initial data when the power is turned on is determined.

In the semiconductor memory device of the present invention, the first
Memory cell and the second memory cell are used as necessary. A first memory cell for outputting the data of the first inverter to the first bit line and outputting the data of the second inverter to the second bit line; and the data of the first inverter for the second bit line The initial data that is different from the second memory cell that outputs the data of the second inverter to the first bit line can be determined, so that the desired initial data can be set when the power is turned on. can do.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments thereof. FIG. 9 is a circuit diagram of the memory cell according to the first embodiment. FIG. 9B is configured so that only the connection relationship to the bit line of the memory cell circuit is different from that of FIG. 9A.

FIGS. 10 (a) and 10 (b) are layout diagrams of the memory cell realizing the circuit diagram shown in FIG. 9 (a).
9B is a layout diagram of a memory cell realizing the circuit diagram shown in FIG. 9B. Two configurations are possible for each of FIG. 9 (a) and FIG. 9 (b). Although not shown in FIG. 9A, a transistor 6c exists on the gate array as shown in FIGS. 10A and 10B. This transistor 6c
Has its gate connected to the power supply line VDD and is in an OFF state. Similarly, as shown in FIGS. 11 (a) and 11 (b),
The transistor 6c is in the OFF state. Also, FIG.
0 and FIG. 11, the source and drain regions of the transistor are omitted in order to avoid complication of the drawing.

In FIG. 9A and FIGS. 10A and 10B, 6
b, 6a and 6d are first, second and third P-channel transistors, and 7b, 7a, 7c and 7d are first, second, third and fourth N-channel transistors. The sources of the P-channel transistors 6a and 6d are connected to the power supply line VDD, and the gates and drains of the P-channel transistors 6a and 6d are connected in parallel with each other. An N-channel transistor 7a is connected in series to the P-channel transistors 6a and 6d with their gates and drains in common, and the source of the N-channel transistor 7a is connected to the ground line GRD. In addition, P is connected to the power supply line VDD.
The source of the channel transistor 6b is also connected, and the gate and drain thereof are commonly connected in series. N done
It is connected to the ground line GRD via the channel transistor 7b.

The P-channel transistor 6b and the N-channel transistor 7b constitute a first inverter circuit,
The P-channel transistors 6a and 6d and the N-channel transistor 7a form a second inverter circuit. The first and second inverter circuits are connected in parallel, and the drain section and the gate section of the first inverter circuit are connected to the gate section and the drain section of the second inverter circuit, respectively. The input part of such an inverter circuit is the respective gate connection part, and the output part is the respective drain connection part. The first and second inverter circuits have their output parts connected to other input parts, and form a data holding loop.

The drain connection of the first inverter circuit is connected to the source of the third N-channel transistor 7c,
Its drain is connected to the first bit line BIT. Further, the drain connection part of the second inverter circuit is connected to the source of the fourth N-channel transistor 7d, and the drain thereof is connected to the second inverted bit line #BIT. The N-channel transistor 7c and the N-channel transistor 7d are connected to the word line WL at the common connection part of their gates. The memory cell circuit configured in this way is called a memory cell A.

In FIG. 9B and FIGS. 11A and 11B, 6
Reference numerals a, 6b and 6c are first, second and third P-channel transistors, and reference numerals 7a, 7b, 7d and 7c are first, second, third and fourth N-channel transistors. The P-channel transistor 6a and the N-channel transistor 7a form a first inverter circuit, and the P-channel transistors 6b and 6c and the N-channel transistor 7b form a second inverter circuit. The P-channel transistor 6b and the P-channel transistor 6c are connected in parallel with their sources, gates and drains in common. The drain connection portion of the first inverter circuit is connected to the source of the third N-channel transistor 7c, and its drain is connected to the second inverted bit line #BIT. The drain connecting portion of the second inverter circuit is connected to the source of the fourth N-channel transistor 7d, and its drain is connected to the first bit line BIT. Other than that, Fig. 9 (a)
The memory cell A is the same as the memory cell A shown in FIG. Then, the memory cell circuit configured in this manner is referred to as a memory cell B.

The memory cells A and B having the above structure are
There is a characteristic difference between each of the first inverter circuit and the second inverter circuit. For example, a case of comparing logic voltage thresholds will be described. FIG. 12 is a graph showing the input / output voltage characteristics of the inverter circuit. When the power is turned on, the first inverter circuit having two P-channel transistors connected in parallel has one more P-channel transistor turned on than the second inverter circuit having one P-channel transistor. Therefore, as shown in FIG. 12, in the transition state, the output voltage of the first inverter circuit becomes higher than the output voltage of the second inverter circuit for the same input voltage.

From this, when the logic voltage threshold is defined as the input voltage when the output voltage becomes half the output voltage, the logic voltage threshold of the first inverter circuit is V ₁ , and It can be said that the logical voltage threshold of the two-inverter circuit is V _{2 and} the logical voltage threshold of the first inverter circuit is lower than that of the second inverter circuit. For this reason,
When the power is turned on, the first inverter circuit having a low logic voltage threshold first outputs the “L” level, and the output of the second inverter circuit can be determined to be the “H” level.

FIG. 13 is a circuit diagram in which the memory cells A and B shown in FIGS. 9A and 9B are connected. The memory cell A having the word line WL (n) and the memory cell B having the word line WL (m) are commonly connected to the bit line BIT and the inverted bit line #BIT. The output point of the first inverter circuit of the memory cell A is X point, and the output point of the second inverter circuit is Y point.
, The output point of the first inverter circuit of the memory cell B is Z
And the output point of the second inverter circuit is U point.

When power is applied to such a memory cell circuit, the potentials at points X and Z become "L" level, and the potentials at points Y and U become "H" level. Word line WL
When (n) is set to "H" level, "L" level which is the initial data of the memory cell A is output to the bit line BIT and "H" level is output to the inverted bit line #BIT. When the word line WL (m) is set to "H" level, "H" level which is the initial data of the memory cell B is output to the bit line BIT and "L" level is set to the inverted bit line #BIT. Is output. Therefore, the memory cell A and the memory cell B of the first embodiment can determine the initial data when the power is turned on, and the read initial data has different logic levels in the memory cell A and the memory cell B. It turns out that

Next, a second embodiment will be described with reference to the drawings showing this. FIG. 14 is a configuration diagram of a semiconductor memory device using the memory cell of the first embodiment. As shown in FIG. 14 (a), memory cells 17, 17 ... Indicated by A / B are arranged side by side in a matrix. This memory cell 17 is the first memory cell A or the second memory cell B shown in the first embodiment. Then, an X decoder (word line decoder) 10, a write / read circuit 11, and a Y decoder 12 are formed, and this semiconductor memory device corresponds to a memory cell 17 selected by the X decoder 10 and the Y decoder 12. ,
The write / read circuit 11 is configured to perform a write operation or a read operation.

Further, as shown in FIG. 14B, the conventional memory cells 9, 9 ... Indicated by M and the memory cells 17, 17 ... Indicated by A / B are mixed and arranged in parallel in a matrix. ing. Others are the same as those in FIG. 14 (a), and the same parts are denoted by the same reference numerals and the description thereof will be omitted.

In such a semiconductor memory device, the initial data of the A / B memory cell 17 is fixed when the power is turned on. In the semiconductor memory device shown in FIG. 14A, the A / B memory cell circuit of the present invention is used for all the memory cells, and the initial data of all the memory cells is fixed. 14
In the semiconductor memory device shown in (b), the conventional M memory cell 9 and the A / B memory cell 17 of the present invention are mixed, and the memory cell for which it is not necessary to determine the initial data is the conventional M memory cell. The memory cell 9 is used. By using the memory cell A or B according to the desired initial data for the memory cell for which the initial data needs to be determined,
The desired data is determined when the power is turned on.

Such a semiconductor memory device has a function of a ROM (read only memory) capable of setting initial data, and also has a function of a read / write memory capable of rewriting data as needed.

[0033]

As described above, in the memory cell and the semiconductor memory device of the present invention, the characteristics of the first inverter circuit and the second inverter circuit are made different from each other, so that the memory cell Initial data can be established. In addition, the present invention has excellent effects such that a semiconductor memory device in which initial data is set when power is turned on can be provided by including the first memory cell and the second memory cell of the present invention. ..

[Brief description of drawings]

FIG. 1 is a schematic plan view of a conventional semiconductor integrated circuit device having a CMOS gate array.

FIG. 2 is an enlarged plan view of one conventional basic cell row.

FIG. 3 is an equivalent circuit diagram of the basic cell row shown in FIG.

FIG. 4 is a conceptual diagram in the case of configuring a semiconductor memory device on a conventional CMOS gate array.

FIG. 5 is a configuration diagram of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram of a conventional memory cell 9.

FIG. 7 is a layout diagram of a conventional memory cell circuit.

FIG. 8 is a layout diagram of a conventional memory cell circuit.

FIG. 9 is a circuit diagram of a memory cell according to the first embodiment.

FIG. 10 is a layout diagram of a memory cell according to the first embodiment.

FIG. 11 is a layout diagram of a memory cell according to the first embodiment.

FIG. 12 is a graph showing input / output voltage characteristics of an inverter circuit.

FIG. 13 is a circuit diagram in which the memory cells of the first embodiment are connected.

FIG. 14 is a configuration diagram of a semiconductor memory device of a second embodiment.

[Explanation of symbols]

 9 Conventional memory cell 17 Memory cell of the present invention 6a, 6b, 6c, 6d P-channel transistor 7a, 7b, 7c, 7d, N-channel transistor A First memory cell B Second memory cell BIT Bit line (first Bit line) #BIT Inverted bit line (second bit line) VDD Power line GRD Ground line

Claims (2)

[Claims] 1. A CMOS gate array is provided for writing data set in a bit line to a first inverter circuit and a second inverter circuit connected in parallel and reading the held data in the bit line. A first P-channel transistor and a first N-channel transistor in the formed memory cell.
Inverter circuit, the second and third P-channel transistors and the second N-channel transistor formed by the second N-channel transistor, and the third and fourth N-channel transistor connected to the bit line The sources of the first, second and third P-channel transistors are connected to a power source, the sources of the first and second N-channel transistors are grounded, and the first N-channel transistor and the first N-channel transistor The drain of the P-channel transistor, the source of the third N-channel transistor, the gate of the second N-channel transistor, and the gates of the second and third P-channel transistors are commonly connected, and the second N-channel transistor is connected. Drain, the drains of the second and third P-channel transistors, the fourth The source of the N-channel transistor and the gates of the first N-channel transistor and the first P-channel transistor are connected in common, and the third and fourth N-channel transistors are connected in common to their respective gates. A memory cell characterized by being configured as follows. 2. The data set in the first and second bit lines is written to the first inverter circuit and the second inverter circuit connected in parallel, and the held data is stored in the first and second inverter circuits. In a semiconductor memory device having a plurality of memory cells configured by a CMOS gate array to read to the bit line of, the drain of the third N-channel transistor is connected to the first bit line, and the fourth N-channel transistor is connected. The memory cell according to claim 1, wherein the drain of the channel transistor is connected to the second bit line, and the drain of the third N channel transistor is connected to the second bit line, The memory cell according to claim 1, wherein the drain of an N-channel transistor is connected to the first bit line, and at least one of A semiconductor memory device comprising a number of semiconductor memory devices.