JPS621265A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the speed of the access time by forming a low- concentration impurity region having the same conduction type as a high- concentration semiconductor substrate onto one conduction type high- concentration semiconductor substrate and shaping a collector region, a base region and an emitter region onto the low-concentration impurity layer in succession. CONSTITUTION:A P-type low-concentration impurity layer 12 is formed to the whole surface or selected surface of a P-type high-concentration impurity semiconductor substrate 11 and N-type buried layers 13 and P-type buried layers 14 are shaped selectively onto the low-concentration impurity layer 12, an N-type epitaxial layer 15 is grown, and a collector region is shaped. Oxide films 16 are formed selectively to the epitaxial layer 15 to electrically isolate unit memory cells, P-type base regions 17 are shaped into several element region, and N-type emitter regions 18 are formed. These emitter regions 18 are connected in a row by a digit line D consisting of an aluminum wire through inter-layer insulating films 19. Accordingly, the thyristor effect of parasitic transistors generated among the memory cells is prevented while junction capacitance is reduce, thus increasing the speed of the access time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a programmable read-only memory device in which information can be reliably written.

[Conventional technology]

Programmable destructive read-only storage (Pro
gramable Read 0nly Memory
(hereinafter referred to as FROM) are classified into two types depending on the structure of the unit memory element. One type is FROM, which uses a fuse and one PN junction connected to it as a unit memory element, and writes information by blowing the fuse.The other type uses a fuse and one PN junction connected to it as a unit memory element, and writes information by blowing the fuse. This is a junction destruction type FROM in which information is written.

FIG. 2 shows a cross-sectional structure of a unit memory element of the junction breakdown type FROM. For example, a high concentration N-type buried layer 23 and a high concentration P-type buried layer 24 are selectively formed on a P-type semiconductor substrate 21. Further, an N-type epitaxial layer 25 is grown on the substrate 21 to form a collector region. Further, an oxide film 26 is selectively formed on this epitaxial layer 25 to electrically isolate unit memory elements, a P-type base region 27 is formed in the region of the epitaxial layer 25, and an N-type emitter is further formed on the P-type base region 27. A region 28 is formed to form unit storage elements Ql and Q! It consists of Each emitter region 28 of the unit memory element is arranged in a row (
Configure the digit wire by wiring in the direction along the plane shown in the figure.
Further, the N-type buried layers 23 are connected in a line perpendicular to the drawing to form word lines W, , W,.

In this unit memory element structure, when a write current is applied to a memory element selected by the digit line and word line, the PN junction between the emitter and the base of the selected memory element is destroyed, and information is written into this memory element. It will be done. For example, in the equivalent circuit of FIG. 3, if information is to be written to the unit storage element Q, the digit line and the word
Write current between z! . When the current is passed, the current flows through the path A, destroys the emitter of the unwritten unit storage element Q8, and information is written there.

[Problem that the invention seeks to solve]

However, in this storage device, if a written unit storage element Q exists on the word line W1 next to this unwritten unit storage element Q2, a part of the write current 1w flows through the path B, Information may not be normally written to the unwritten unit storage element Q2, and a writing failure may occur.

This is because the parasitic PNP I-transistor Q3, which is composed of the base region of the unwritten unit storage element Q2, the N-type buried layer, and the P-type semiconductor substrate, supplies a write current I to the unwritten unit storage element Q2. It works when I start flowing,
Therefore, carriers are accumulated in the P-type semiconductor substrate, and since the resistance bone R of the semiconductor substrate is high, the semiconductor substrate potential at point X rises, and the N-type buried layer of the unwritten unit memory element Q2 and the P-type semiconductor substrate and Written unit memory element Q.

This is because the parasitic NPN transistor Q4 is operated with the N-type buried layer, and a so-called parasitic thyristor effect occurs.

As a result, part of the write current flows through the current path B through the written unit memory element Q, and therefore, information may not be written to the unwritten unit memory element Q2 to which information should be written, or information may not be written to the unwritten unit memory element Q2. Failures occur due to the shortage, leading to a decline in FROM write yield and reliability.

In order to prevent such problems, it is conceivable to increase the impurity concentration of the semiconductor substrate, that is, the P-type semiconductor substrate 21 in FIG. 2, to lower its specific resistance and to reduce the resistance bone R. In other words, due to the decrease in the resistance bone R, the parasitic PNP transistor Q prevents the semiconductor substrate potential from rising at point X due to the carriers injected and accumulated into the semiconductor substrate. This is a method to prevent the thyristor effect. However, increasing the impurity concentration of the semiconductor substrate increases the junction capacitance with the highly doped N-type buried layer, resulting in a problem of reduced access time.

In addition, as another countermeasure, a low concentration of P is applied on a P-type semiconductor substrate.
A method of depositing a type epitaxial layer and forming an N type buried layer on this epitaxial layer is also considered. For example, FIG. 4 shows the concentration profile, and the horizontal axis represents the depth.
The vertical axis shows the impurity concentration, χ41 is the N-type buried layer region, χ
4. is a P-type epitaxial layer region, χ4. is a P-type semiconductor substrate region. With this configuration, it is possible to reduce the junction capacitance between the buried layer and the epitaxial layer, reduce the resistance bone, and prevent the semiconductor substrate potential from rising. However, a structure in which a low-concentration P-type epitaxial layer is formed on a P-type semiconductor substrate is difficult to manufacture and expensive, and it is difficult to apply it to -M.

[Means for Solving the Problems] The semiconductor memory device of the present invention prevents the parasitic thyristor effect and suppresses the increase in junction capacitance, thereby improving reliability of information writing and speeding up access time. For this purpose, a low concentration impurity layer of the same conductivity type is formed on a high concentration semiconductor substrate of one conductivity type, and a collector region, a base region and an emitter region are sequentially formed on this low concentration impurity layer. This is the manufacturing method.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a unit memory element of a FROM to explain one embodiment of the present invention, and the manufacturing process thereof will be explained below.

For example, N-type impurities are introduced into the entire surface or a selected surface of the P-type high-concentration impurity semiconductor substrate 11 by ion implantation or the like to form the P-type low-concentration impurity layer 12 . and,
An N-type buried layer 13 and a P-type buried layer 14 are selectively formed on this low concentration impurity layer 12, and an N-type epitaxial layer 15 is further grown thereon to form a collector region.

Next, an oxide film 16 is selectively formed on this epitaxial layer 15 to electrically isolate the unit memory elements. Then, a P-type base region 17 is formed in each element region, and an N-type emitter region 18 is further formed thereon. Needless to say, these emitter regions 18 are connected in a line through an interlayer insulating film 19 by digit lines made of aluminum wires.

In FIG. 5, which shows the concentration profiles of the P-type high-concentration impurity semiconductor substrate 11, the P-type low-concentration impurity layer 12, and the N-type buried layer 13, χ and 1 are the N-type buried layer 13 region, χ , 2 is a P-type low concentration impurity layer 12fil region, χ3. is the semiconductor substrate 11fii area. As you will see,
The concentration at the point where the N-type buried layer 13 contacts the P-type low concentration impurity layer 12 is approximately the same as the concentration at the junction point of the N-type buried layer in the P-type epitaxial layer shown in FIG.

According to the above configuration, the parasitic PNP as shown in FIG.
) Even if transistor Q is generated and carriers are to be injected and accumulated, the semiconductor The resistance bone R of the substrate is reduced, and the potential rise at point X does not occur even when carriers are injected and accumulated.

Therefore, the parasitic NPN) transistor Q4 does not operate, and even if the written unit symbol element Q exists on the word line adjacent to the unwritten unit storage element Q2, normal information can be written.

Incidentally, compared to the resistance R of 500Ω in the case of a conventional P-type semiconductor substrate with an impurity concentration of IQ"cm-', in this example, by using a high-concentration semiconductor substrate 11 with an impurity concentration of 5X1O"cm-', , the resistance bone R can be suppressed to 50Ω or less.

On the other hand, in the present invention, since the N-type buried layer 13 is formed on the low concentration impurity layer 12, the junction capacitance between the two can be significantly reduced, and access time can be increased. That is,
When an N-type buried layer is directly formed on a P-type semiconductor substrate with an impurity concentration of 5X10"cm-3, the junction capacitance is 309F, but in this example, the concentration of the P-type low concentration impurity layer 12 is I
If QISam-' is used, the junction capacitance can be reduced to topp, and the access time can be reduced to 15 μm compared to the former's 25 μm.
It can be speeded up.

Therefore, in terms of reducing the resistance bone R and reducing the junction capacitance, it is possible to obtain an effect that is comparable to that of a structure using a P-type epitaxial layer, and it can be manufactured easily and inexpensively.

〔Effect of the invention〕

As explained above, according to the present invention, a low concentration impurity layer is formed on a high concentration semiconductor substrate, and a collector layer is formed on this layer.
Since the base and emitter regions are formed, it is possible to prevent the thyristor effect of the parasitic transistor that occurs between the storage elements, reduce the junction capacitance, achieve faster access time, and improve the write yield. A highly reliable, high-speed semiconductor memory device can be obtained at low cost.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the semiconductor memory device of the present invention, FIG. 2 is a cross-sectional view of a conventional structure, FIG. 3 is an equivalent circuit diagram for explaining the parasitic silicon risk effect, and FIG. 4 is a structure using an epitaxial layer. FIG. 5 is a concentration profile diagram of the present invention. 11...P-type high concentration semiconductor substrate, 12...P-type low concentration impurity layer, 13.23-...N-type buried layer, 14.24
...P type buried layer, 15.25...N type epitaxial layer (collector region), 16.26...Oxide film, 17
．． 27...P-type base region, 18.28...N-type emitter region, 21...P-type semiconductor substrate, D...digital 7) line, W,, Wt...word line, Ql. ...written unit memory element, Q2... unwritten unit memory element, Q3... parasitic PNP) transistor, Q4... parasitic NPN transistor, I,... write current, R.
...Resistance bones of semiconductor substrates. Figure 1 i3: N9 buried bl'v 1B-N Semi, 74
1-14-P Daenomoru Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] 1. A low concentration impurity layer of the same conductivity type is formed on a high concentration semiconductor substrate of one conductivity type, and a collector region having a buried layer of the opposite conductivity type is formed on this low concentration impurity layer. A semiconductor memory device comprising: a base region and an emitter region formed thereon in order to constitute a unit memory element. 2. A step of introducing an opposite conductivity type impurity into a high concentration semiconductor substrate of one conductivity type to form a low concentration impurity layer of the same conductivity type on this semiconductor substrate, and embedding the opposite conductivity type on this low concentration impurity layer. forming a collector region by depositing an epitaxial layer of opposite conductivity type on the epitaxial layer; forming a base region of one conductivity type on the epitaxial layer; and depositing an epitaxial layer of opposite conductivity type on the epitaxial layer; 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a conductive type emitter region.