JPS6435945A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6435945A JPS6435945A JP62191774A JP19177487A JPS6435945A JP S6435945 A JPS6435945 A JP S6435945A JP 62191774 A JP62191774 A JP 62191774A JP 19177487 A JP19177487 A JP 19177487A JP S6435945 A JPS6435945 A JP S6435945A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- cell region
- regions
- decoders
- sectioned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To contrive to facilitate the layout of a semiconductor integrated circuit by a method wherein two pieces of first and second memory cell regions are provided and the number of the memory cells of the second memory cell region is decreased than the number of the memory cells of the first memory cell region. CONSTITUTION:An entire memory cell region 4 constituted on a chip is constituted of four pieces of first memory cell regions 1a, which are sectioned by first line decoders 2a and first row decoders 3a, and two pieces of second memory cell regions 1b, which are sectioned by second line decoders 2b and a second low decoder 3b. In such a way, the number of memory cells of the memory cell regions, which are sectioned by the fine decoders and the row decoders within the. entire memory cell region, is decreased than the number of memory cells of at least one piece of the memory cell region. Thereby, a space can be made at the regions between the memory cell region and the external sides of the chip without changing the unidirectional size of the chip and its becomes possible to arrange a peripheral circuit element and bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62191774A JPS6435945A (en) | 1987-07-30 | 1987-07-30 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62191774A JPS6435945A (en) | 1987-07-30 | 1987-07-30 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6435945A true JPS6435945A (en) | 1989-02-07 |
Family
ID=16280307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62191774A Pending JPS6435945A (en) | 1987-07-30 | 1987-07-30 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6435945A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04281062A (en) * | 1990-01-12 | 1992-10-06 | Akzo Nv | Method for manufacture of closely woven, cover- free industrial textile and article consisting of said textile |
| US6545900B2 (en) | 2000-09-12 | 2003-04-08 | Infineon Technologies, Ag | MRAM module configuration |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214559A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS62122139A (en) * | 1985-11-21 | 1987-06-03 | Nec Corp | Semiconductor memory device |
-
1987
- 1987-07-30 JP JP62191774A patent/JPS6435945A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214559A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS62122139A (en) * | 1985-11-21 | 1987-06-03 | Nec Corp | Semiconductor memory device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04281062A (en) * | 1990-01-12 | 1992-10-06 | Akzo Nv | Method for manufacture of closely woven, cover- free industrial textile and article consisting of said textile |
| US6545900B2 (en) | 2000-09-12 | 2003-04-08 | Infineon Technologies, Ag | MRAM module configuration |
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