JPS6457486A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6457486A
JPS6457486A JP62214715A JP21471587A JPS6457486A JP S6457486 A JPS6457486 A JP S6457486A JP 62214715 A JP62214715 A JP 62214715A JP 21471587 A JP21471587 A JP 21471587A JP S6457486 A JPS6457486 A JP S6457486A
Authority
JP
Japan
Prior art keywords
sram
memory cell
column
disposed
decoder circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62214715A
Other languages
Japanese (ja)
Inventor
Masaaki Kubodera
Kimiko Nishizawa
Masahiro Shioya
Katsuro Sasaki
Takao Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62214715A priority Critical patent/JPS6457486A/en
Priority to KR1019880010509A priority patent/KR890004327A/en
Publication of JPS6457486A publication Critical patent/JPS6457486A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To reduce the consuming power of a SRAM, by dividing the memory cell array of the SRAM into 32 in the direction of a column and disposing a row recorder circuit in the central part thereof. CONSTITUTION:In the SRAM, the memory cell array is divided into at least 32 in the extending direction of a word line, the row decoder circuit R-DC is disposed at the center part thereof and a column switch CSW, a column decoder circuit CDC, etc., are disposed on the one end part of the individual divided memory cell arrays. External terminals P are disposed at the four sides of rectangular semiconductor chips constituting the SRAM and the two sets of the column switches CSW are controlled by one column decoder circuit CDC. Thereby, the quantity of a current passing from a load circuit to the memory cell can be reduced to 1/32 to reduce the consuming power of the SRAM and attain the high speed of the operating speed of the SRAM.
JP62214715A 1987-08-28 1987-08-28 Semiconductor integrated circuit device Pending JPS6457486A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62214715A JPS6457486A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device
KR1019880010509A KR890004327A (en) 1987-08-28 1988-08-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62214715A JPS6457486A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6457486A true JPS6457486A (en) 1989-03-03

Family

ID=16660420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62214715A Pending JPS6457486A (en) 1987-08-28 1987-08-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6457486A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03232270A (en) * 1989-08-30 1991-10-16 Nec Corp Semiconductor memory device
KR100296561B1 (en) * 1997-02-26 2001-08-07 니시무로 타이죠 Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03232270A (en) * 1989-08-30 1991-10-16 Nec Corp Semiconductor memory device
KR100296561B1 (en) * 1997-02-26 2001-08-07 니시무로 타이죠 Semiconductor memory

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