JPS5740951A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5740951A
JPS5740951A JP55116868A JP11686880A JPS5740951A JP S5740951 A JPS5740951 A JP S5740951A JP 55116868 A JP55116868 A JP 55116868A JP 11686880 A JP11686880 A JP 11686880A JP S5740951 A JPS5740951 A JP S5740951A
Authority
JP
Japan
Prior art keywords
chips
monitor
series
several
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55116868A
Other languages
English (en)
Other versions
JPS6262051B2 (ja
Inventor
Takeshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55116868A priority Critical patent/JPS5740951A/ja
Publication of JPS5740951A publication Critical patent/JPS5740951A/ja
Publication of JPS6262051B2 publication Critical patent/JPS6262051B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
JP55116868A 1980-08-25 1980-08-25 Manufacture of semiconductor device Granted JPS5740951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55116868A JPS5740951A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55116868A JPS5740951A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5740951A true JPS5740951A (en) 1982-03-06
JPS6262051B2 JPS6262051B2 (ja) 1987-12-24

Family

ID=14697612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55116868A Granted JPS5740951A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5740951A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6037138A (ja) * 1983-08-08 1985-02-26 Nec Corp 半導体集積回路装置
JPS6338239A (ja) * 1986-08-04 1988-02-18 Nec Kyushu Ltd 半導体装置の製造方法
JPS6349237U (ja) * 1986-09-16 1988-04-04
JPS63220537A (ja) * 1987-03-09 1988-09-13 Nec Corp 半導体基板
US5561373A (en) * 1990-10-09 1996-10-01 Fujitsu Limited Method and device for detecting electrostatic stress applied to a product semiconductor device during each production process
EP0709892A3 (en) * 1994-09-30 1998-11-04 Yozan Inc. MOS inverter forming method
JP2006120962A (ja) * 2004-10-25 2006-05-11 Nec Electronics Corp 半導体装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4919029A (ja) * 1972-03-27 1974-02-20
JPS54129991A (en) * 1978-03-31 1979-10-08 Nec Corp Manufacture of mesa-structure semiconductor device
JPS54157479A (en) * 1978-06-02 1979-12-12 Hitachi Ltd Electrode terminal forming method to wiring connecting semiconductor elements

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4919029A (ja) * 1972-03-27 1974-02-20
JPS54129991A (en) * 1978-03-31 1979-10-08 Nec Corp Manufacture of mesa-structure semiconductor device
JPS54157479A (en) * 1978-06-02 1979-12-12 Hitachi Ltd Electrode terminal forming method to wiring connecting semiconductor elements

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6037138A (ja) * 1983-08-08 1985-02-26 Nec Corp 半導体集積回路装置
JPS6338239A (ja) * 1986-08-04 1988-02-18 Nec Kyushu Ltd 半導体装置の製造方法
JPS6349237U (ja) * 1986-09-16 1988-04-04
JPS63220537A (ja) * 1987-03-09 1988-09-13 Nec Corp 半導体基板
US5561373A (en) * 1990-10-09 1996-10-01 Fujitsu Limited Method and device for detecting electrostatic stress applied to a product semiconductor device during each production process
EP0709892A3 (en) * 1994-09-30 1998-11-04 Yozan Inc. MOS inverter forming method
JP2006120962A (ja) * 2004-10-25 2006-05-11 Nec Electronics Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPS6262051B2 (ja) 1987-12-24

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