JPS5735345A - Multilayer wiring structure and manufacturing method of the same - Google Patents

Multilayer wiring structure and manufacturing method of the same

Info

Publication number
JPS5735345A
JPS5735345A JP11052980A JP11052980A JPS5735345A JP S5735345 A JPS5735345 A JP S5735345A JP 11052980 A JP11052980 A JP 11052980A JP 11052980 A JP11052980 A JP 11052980A JP S5735345 A JPS5735345 A JP S5735345A
Authority
JP
Japan
Prior art keywords
insulation film
layer
multilayer wiring
wiring structure
molecular weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11052980A
Other languages
Japanese (ja)
Inventor
Atsushi Endo
Toshio Yada
Yuji Hizuka
Torahiko Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11052980A priority Critical patent/JPS5735345A/en
Publication of JPS5735345A publication Critical patent/JPS5735345A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent disconnection, by a method wherein heat-resistant high molecular weight material is used as an interlayer insulator of a multilayer wiring structure composed on a semiconductor substrate so that a flat insulation film with very few pin-holes is formed. CONSTITUTION:Semiconductor grade polyimide resin is applied over a ceramics substrate 9 by spinning and an insulation film 10 is formed by thermal drying process. Al circuit pattern 11 is formed on te film 10 and the polyimide resin is again applied so as to form an insulation film layer 12. Then an aperture 13 is formed in the insulation film layer 12 by photoetching and the 2nd wiring layer 14 is formed by Al evaporation. Thus, as high molecular weight material is used as the layer insulation 12, pin-holes are not generated and difference in level is eliminated by high flattness so that disconnection of the circuit is prevented.
JP11052980A 1980-08-12 1980-08-12 Multilayer wiring structure and manufacturing method of the same Pending JPS5735345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11052980A JPS5735345A (en) 1980-08-12 1980-08-12 Multilayer wiring structure and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11052980A JPS5735345A (en) 1980-08-12 1980-08-12 Multilayer wiring structure and manufacturing method of the same

Publications (1)

Publication Number Publication Date
JPS5735345A true JPS5735345A (en) 1982-02-25

Family

ID=14538111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11052980A Pending JPS5735345A (en) 1980-08-12 1980-08-12 Multilayer wiring structure and manufacturing method of the same

Country Status (1)

Country Link
JP (1) JPS5735345A (en)

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