JPS5612764A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device

Info

Publication number
JPS5612764A
JPS5612764A JP8886879A JP8886879A JPS5612764A JP S5612764 A JPS5612764 A JP S5612764A JP 8886879 A JP8886879 A JP 8886879A JP 8886879 A JP8886879 A JP 8886879A JP S5612764 A JPS5612764 A JP S5612764A
Authority
JP
Japan
Prior art keywords
resistance layer
protective film
etching method
semiconductor element
resin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8886879A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tsuji
Shigetoshi Takayanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8886879A priority Critical patent/JPS5612764A/en
Publication of JPS5612764A publication Critical patent/JPS5612764A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable formation of a protective film of a semiconductor element and a protective film of a resistance layer independently by forming a resistance layer after all the semiconductor elements, excluding the resistance layer, have been formed. CONSTITUTION:A semiconductor element 2 is formed on a semiconductor substrate 1 besides a resistance layer. Then, a polyimide heat-resisting high molecular resin film 8 is applied on the whole surface. Next, openings 9 and 10 are provided on the resin film 8 using a photo etching method and the joined section with the resistance layer and the connection wiring layers 5 and 7 are exposed. Subsequently, a resistance layer is formed using an evaporation method and a resistance layer pattern 11 is formed employing a photo etching method.
JP8886879A 1979-07-12 1979-07-12 Manufacturing method for semiconductor device Pending JPS5612764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8886879A JPS5612764A (en) 1979-07-12 1979-07-12 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8886879A JPS5612764A (en) 1979-07-12 1979-07-12 Manufacturing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5612764A true JPS5612764A (en) 1981-02-07

Family

ID=13954980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8886879A Pending JPS5612764A (en) 1979-07-12 1979-07-12 Manufacturing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5612764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210411A (en) * 1982-06-02 1983-12-07 Sharp Corp Detector for imperfect combustion

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210411A (en) * 1982-06-02 1983-12-07 Sharp Corp Detector for imperfect combustion
JPH033124B2 (en) * 1982-06-02 1991-01-17 Sharp Kk

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