JPS5730018A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS5730018A
JPS5730018A JP10467580A JP10467580A JPS5730018A JP S5730018 A JPS5730018 A JP S5730018A JP 10467580 A JP10467580 A JP 10467580A JP 10467580 A JP10467580 A JP 10467580A JP S5730018 A JPS5730018 A JP S5730018A
Authority
JP
Japan
Prior art keywords
input
count value
channel
output
ioc3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10467580A
Other languages
Japanese (ja)
Inventor
Ikuro Koyanazu
Satoshi Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10467580A priority Critical patent/JPS5730018A/en
Publication of JPS5730018A publication Critical patent/JPS5730018A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To speed up the operation of data transfer, by collating the number of transmitted/received data at an input/output channel and an input/output controller IOC mutually at the end of transfer. CONSTITUTION:Every time when an input/output channel 2 and an input/output controller IOC3 transmit or receive data to or from an input and output interface, they subtract the count value of registers 21, 31 and renew it. The data transfer is finished when the count value is at ''O'' to the channel 2 ot the IOC3, the IOC3 makes a continuous transfer indicating signal 6 to ''1'' and transfers the content of count stored in a status byte and a resistor 31 to the input/output channel continuously. The channel 2 collated a count value transmitted with a count value in the register 21 to check if the data transfer is normally performed.
JP10467580A 1980-07-30 1980-07-30 Input and output control system Pending JPS5730018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10467580A JPS5730018A (en) 1980-07-30 1980-07-30 Input and output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10467580A JPS5730018A (en) 1980-07-30 1980-07-30 Input and output control system

Publications (1)

Publication Number Publication Date
JPS5730018A true JPS5730018A (en) 1982-02-18

Family

ID=14387041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10467580A Pending JPS5730018A (en) 1980-07-30 1980-07-30 Input and output control system

Country Status (1)

Country Link
JP (1) JPS5730018A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60101660A (en) * 1983-11-08 1985-06-05 Usac Electronics Ind Co Ltd Input/output controlling system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991342A (en) * 1972-12-29 1974-08-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991342A (en) * 1972-12-29 1974-08-31

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60101660A (en) * 1983-11-08 1985-06-05 Usac Electronics Ind Co Ltd Input/output controlling system
JPH0219498B2 (en) * 1983-11-08 1990-05-02 Pfu Ltd

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