JPS57172438A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS57172438A
JPS57172438A JP5764181A JP5764181A JPS57172438A JP S57172438 A JPS57172438 A JP S57172438A JP 5764181 A JP5764181 A JP 5764181A JP 5764181 A JP5764181 A JP 5764181A JP S57172438 A JPS57172438 A JP S57172438A
Authority
JP
Japan
Prior art keywords
data transfer
input
speed
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5764181A
Other languages
Japanese (ja)
Other versions
JPH042981B2 (en
Inventor
Joji Kikuchi
Toshiyuki Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5764181A priority Critical patent/JPS57172438A/en
Publication of JPS57172438A publication Critical patent/JPS57172438A/en
Publication of JPH042981B2 publication Critical patent/JPH042981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Abstract

PURPOSE:To achieve stable and high-speed data transfer, by discriminating an input and output device during data transfer and controlling the data transfer speed between channel devices and data buffer circuits with the discrimination signal. CONSTITUTION:In input and output operation to input/output devices 301-303, the selection of an input/ourput device is instructed from a channel device 10 and the information indicating the type of the selected input/output device is stored in an I/O discriminating information register 24 of an input/output controller 20. At data transfer, a speed control timer 25 is controlled with contents ID of the register 24 and the timer 25 generates a timing signal V with a time interval corresponding to the data transfer speed required by the input/output device during data transfer at present, repetitively. A signal V of a data transfer main control circuit 22 controls a data buffer circuit 21 and makes data transfer on a data bus BUS in a transfer speed almost concident with the data transfer speed on a common data bus BUS', and a device 21 operates to absorb the response fluctuation of the device 10.
JP5764181A 1981-04-16 1981-04-16 Data transfer controller Granted JPS57172438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5764181A JPS57172438A (en) 1981-04-16 1981-04-16 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5764181A JPS57172438A (en) 1981-04-16 1981-04-16 Data transfer controller

Publications (2)

Publication Number Publication Date
JPS57172438A true JPS57172438A (en) 1982-10-23
JPH042981B2 JPH042981B2 (en) 1992-01-21

Family

ID=13061509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5764181A Granted JPS57172438A (en) 1981-04-16 1981-04-16 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS57172438A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62271037A (en) * 1986-05-19 1987-11-25 Fujitsu Ltd Control system for transfer of data
JPS63182765A (en) * 1987-01-23 1988-07-28 Fujitsu Ltd Control system for direct memory access

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62271037A (en) * 1986-05-19 1987-11-25 Fujitsu Ltd Control system for transfer of data
JPS63182765A (en) * 1987-01-23 1988-07-28 Fujitsu Ltd Control system for direct memory access

Also Published As

Publication number Publication date
JPH042981B2 (en) 1992-01-21

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