JPS57164355A - Input and output interface device - Google Patents

Input and output interface device

Info

Publication number
JPS57164355A
JPS57164355A JP56048591A JP4859181A JPS57164355A JP S57164355 A JPS57164355 A JP S57164355A JP 56048591 A JP56048591 A JP 56048591A JP 4859181 A JP4859181 A JP 4859181A JP S57164355 A JPS57164355 A JP S57164355A
Authority
JP
Japan
Prior art keywords
data
input
channel
transfer speed
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56048591A
Other languages
Japanese (ja)
Other versions
JPS6250848B2 (en
Inventor
Joji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56048591A priority Critical patent/JPS57164355A/en
Publication of JPS57164355A publication Critical patent/JPS57164355A/en
Publication of JPS6250848B2 publication Critical patent/JPS6250848B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Abstract

PURPOSE:To control a data transfer speed from a data cash device to an input/ output controller according to a transfer time, by measuring the transfer time of data between a channel and the input/output controller with an input/output device. CONSTITUTION:A data request is outputted from a signal line 22, and a time from the generation of data request to the return of data response given from a signal line 23 is measured to obtain an effective transfer speed. Next, the effective transfer speed is transmitted to a data cash device 16 via a transfer speed informing (SPST) signal line 28. The device 16 transfers data to a channel when the data transfer request from a channel exists in this effective transfer speed. When the 1st data request signal DVDRQ is outputted from the device 16, an input/output controller 14 returns the 1st data response signal DVDRP to the device 16, and the 2nd data request signal CHDRQ is transferred to a channel 13 after the internal delay time of the device 14. The request signal CHDRQ turns off with the leading of the 2nd response signal CHDRP from the channel 13.
JP56048591A 1981-03-31 1981-03-31 Input and output interface device Granted JPS57164355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56048591A JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56048591A JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Publications (2)

Publication Number Publication Date
JPS57164355A true JPS57164355A (en) 1982-10-08
JPS6250848B2 JPS6250848B2 (en) 1987-10-27

Family

ID=12807640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56048591A Granted JPS57164355A (en) 1981-03-31 1981-03-31 Input and output interface device

Country Status (1)

Country Link
JP (1) JPS57164355A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173867A (en) * 1983-03-22 1984-10-02 Fujitsu Ltd Control system for transfer of disk cache data
JPS61281349A (en) * 1985-06-07 1986-12-11 Oki Electric Ind Co Ltd Interface controlling method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS5010127U (en) * 1973-05-24 1975-02-01
JPS50103226A (en) * 1974-01-04 1975-08-15
JPS5422132A (en) * 1977-07-19 1979-02-19 Honeywell Inf Systems Data transfer controller
JPS55157051A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS5010127U (en) * 1973-05-24 1975-02-01
JPS50103226A (en) * 1974-01-04 1975-08-15
JPS5422132A (en) * 1977-07-19 1979-02-19 Honeywell Inf Systems Data transfer controller
JPS55157051A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173867A (en) * 1983-03-22 1984-10-02 Fujitsu Ltd Control system for transfer of disk cache data
JPS6212546B2 (en) * 1983-03-22 1987-03-19 Fujitsu Ltd
JPS61281349A (en) * 1985-06-07 1986-12-11 Oki Electric Ind Co Ltd Interface controlling method
JPH0473182B2 (en) * 1985-06-07 1992-11-20 Oki Electric Ind Co Ltd

Also Published As

Publication number Publication date
JPS6250848B2 (en) 1987-10-27

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