JPS56162126A - Input/output control device - Google Patents

Input/output control device

Info

Publication number
JPS56162126A
JPS56162126A JP6409880A JP6409880A JPS56162126A JP S56162126 A JPS56162126 A JP S56162126A JP 6409880 A JP6409880 A JP 6409880A JP 6409880 A JP6409880 A JP 6409880A JP S56162126 A JPS56162126 A JP S56162126A
Authority
JP
Japan
Prior art keywords
data
cpu
input
output control
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6409880A
Other languages
Japanese (ja)
Inventor
Yasuo Kaneko
Masayuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6409880A priority Critical patent/JPS56162126A/en
Publication of JPS56162126A publication Critical patent/JPS56162126A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent an operation error by writing in an I/O a data row which has added a code for discriminating a selected CPU in accordance with a write request, in an input/output control device for controlling a data transfer between plural CPU's and one I/O. CONSTITUTION:CPU's 1a, 1b are connected to an I/O 2 through an input/output control device 3. The device 3 consists of a switching part 4 and an input/output control part 7. When an operator changes over the switching part 4 to a CPU to which it is desired to input a data, for instance, a CPU1a, and starts it, a data which has been sent together with a data write request from the CPU1a is sent to the control part 7 through a data line 6. The control part 7 checks from a line 8 to which CPU the data has been changed over, generates a discrimination code according to a state which has been changed over, adds it to the data, and write it in the I/O 2. At the time of data readout request, a discrimination code which has been read out from the I/O 2 is compared with a discrimination code by a changed state of the switching part 4, from the line 8, and when they have coincided to each other, the data is outputted to the CPU, and when they have not coincided, an error is displayed.
JP6409880A 1980-05-16 1980-05-16 Input/output control device Pending JPS56162126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6409880A JPS56162126A (en) 1980-05-16 1980-05-16 Input/output control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6409880A JPS56162126A (en) 1980-05-16 1980-05-16 Input/output control device

Publications (1)

Publication Number Publication Date
JPS56162126A true JPS56162126A (en) 1981-12-12

Family

ID=13248253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6409880A Pending JPS56162126A (en) 1980-05-16 1980-05-16 Input/output control device

Country Status (1)

Country Link
JP (1) JPS56162126A (en)

Similar Documents

Publication Publication Date Title
JPS57117027A (en) Signal sending and receiving circuit
JPS56166614A (en) Mixing console
JPS56162126A (en) Input/output control device
JPS5510614A (en) Controller
JPS5694596A (en) Memory control system
JPS56116138A (en) Input and output controller
JPS55157022A (en) Output circuit for microcomputer
JPS5710846A (en) Information processing equipment
JPS5750059A (en) Status history memory system
JPS6482756A (en) Communication equipment
JPS56149626A (en) Channel device
JPS5733472A (en) Memory access control system
JPS57119535A (en) Control station device
JPS5647886A (en) Hard copy control system of display
JPS575141A (en) Bus control system
JPS5757329A (en) Controller of virtual input-output device
JPS56105543A (en) Microprogram controlling system
JPS5771054A (en) Microprogram controller
JPS5491028A (en) Memory control system of multiprocessor system
JPS5361931A (en) Communication control device
JPS54121630A (en) Inter-unit interface system
JPS56168251A (en) Data transfer buffer system
JPS5730020A (en) Memory address controlling system
JPS57197653A (en) Control device of microprogram
JPS5512570A (en) Control system for memory element