JPS57157332A - Input and output control system - Google Patents
Input and output control systemInfo
- Publication number
- JPS57157332A JPS57157332A JP4341581A JP4341581A JPS57157332A JP S57157332 A JPS57157332 A JP S57157332A JP 4341581 A JP4341581 A JP 4341581A JP 4341581 A JP4341581 A JP 4341581A JP S57157332 A JPS57157332 A JP S57157332A
- Authority
- JP
- Japan
- Prior art keywords
- data
- control section
- format
- sector
- share
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To transfer a prescribed amount of data with a simple constitution and to obtain coordination with data on a data buffer, by using the contents of format counter of a format control section with a data transfer control section. CONSTITUTION:A channel 2 is provided with a format control section 3 and a data transfer control section 4, and a value for one sector's share(256-byte) is preset to a format counter(FC) 6 of the format control section 3, -1 is given every time of write of one-byte, a signal ST is given just before the write for one sector's share, and a comparison circuit 11 is made effective. The data transfer control section 4 always manages the number of data bytes present on data buffers 5-0-5-N, the number of bytes BC is compared with the content of the said FC6 at the said comparison circuit, and when the data for one sector's share is transferred on the data buffer, a comparison circuit 10 turns off a gate 9. Thus, the contents of the FC6 can be used by the data transfer control section 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4341581A JPS6024978B2 (en) | 1981-03-25 | 1981-03-25 | input/output control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4341581A JPS6024978B2 (en) | 1981-03-25 | 1981-03-25 | input/output control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57157332A true JPS57157332A (en) | 1982-09-28 |
JPS6024978B2 JPS6024978B2 (en) | 1985-06-15 |
Family
ID=12663080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4341581A Expired JPS6024978B2 (en) | 1981-03-25 | 1981-03-25 | input/output control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6024978B2 (en) |
-
1981
- 1981-03-25 JP JP4341581A patent/JPS6024978B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6024978B2 (en) | 1985-06-15 |
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