JPS5720850A - Pseudo fault generating system - Google Patents

Pseudo fault generating system

Info

Publication number
JPS5720850A
JPS5720850A JP9634880A JP9634880A JPS5720850A JP S5720850 A JPS5720850 A JP S5720850A JP 9634880 A JP9634880 A JP 9634880A JP 9634880 A JP9634880 A JP 9634880A JP S5720850 A JPS5720850 A JP S5720850A
Authority
JP
Japan
Prior art keywords
given
pseudo fault
case
memory module
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9634880A
Other languages
Japanese (ja)
Inventor
Shigeo Kaneda
Toshihiko Sato
Shozo Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP9634880A priority Critical patent/JPS5720850A/en
Publication of JPS5720850A publication Critical patent/JPS5720850A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To realize a pseudo fault generation test using a maintenance test program by means of a simple additional circuit even in case just one centralized control type storage device is used. CONSTITUTION:The information given from a specific memory module designating means 30 which is provided outside a common control logic part 21 and gives an indication to a specific module to produce a pseudo fault plus a memory module designating address which is added in the case of an access of memory are given to an address coincidence deciding circuit 39. Based on the result of decision of the circuit 39, an access is given to the memory module indicated by the means 30. In this case, a pseudo fault is produced. No pseudo fault is produced in case an access is given to the memory module to which no indication is given by the means 30.
JP9634880A 1980-07-15 1980-07-15 Pseudo fault generating system Pending JPS5720850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9634880A JPS5720850A (en) 1980-07-15 1980-07-15 Pseudo fault generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9634880A JPS5720850A (en) 1980-07-15 1980-07-15 Pseudo fault generating system

Publications (1)

Publication Number Publication Date
JPS5720850A true JPS5720850A (en) 1982-02-03

Family

ID=14162493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9634880A Pending JPS5720850A (en) 1980-07-15 1980-07-15 Pseudo fault generating system

Country Status (1)

Country Link
JP (1) JPS5720850A (en)

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