JPS576955A - Information processor - Google Patents

Information processor

Info

Publication number
JPS576955A
JPS576955A JP8019580A JP8019580A JPS576955A JP S576955 A JPS576955 A JP S576955A JP 8019580 A JP8019580 A JP 8019580A JP 8019580 A JP8019580 A JP 8019580A JP S576955 A JPS576955 A JP S576955A
Authority
JP
Japan
Prior art keywords
processor
priority
instruction
selecting circuit
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8019580A
Other languages
Japanese (ja)
Inventor
Akira Ikuta
Masato Suyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP8019580A priority Critical patent/JPS576955A/en
Publication of JPS576955A publication Critical patent/JPS576955A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent a fault of a priority selecting circuit and avoid the deterioraration of process efficiency of a multiprocessor system, by reading the priority selection result signal out of a common memory by an instruction given from a processor. CONSTITUTION:A processor 1-1 executes the priority selection result reading instruction, and at the same time a processor 1-n delivers an access request. Under such conditios, if a priority selecting circuit 5 selects a processor 1-1, this result is set to flip-flops 6-1-5-n and then led to interfaces 4-1-4-n to accept an instruction of the processor 1-1. As a result, a selecting circuit 9 delivers the data of the flip- flops 6-1-6-n to the processor 1-1 in place of the data of a memory 3 by an instruction of a working designating circuit 8. Thus a processor can read the priority selection result, and accordingly whether or not the priority selecting circuit performs a correct selection of priority based on the sequence of priority can be inspected.
JP8019580A 1980-06-16 1980-06-16 Information processor Pending JPS576955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8019580A JPS576955A (en) 1980-06-16 1980-06-16 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8019580A JPS576955A (en) 1980-06-16 1980-06-16 Information processor

Publications (1)

Publication Number Publication Date
JPS576955A true JPS576955A (en) 1982-01-13

Family

ID=13711595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8019580A Pending JPS576955A (en) 1980-06-16 1980-06-16 Information processor

Country Status (1)

Country Link
JP (1) JPS576955A (en)

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