JPS57193041A - Forming method for monitoring circuit of semiconductor element formed on semiconductor substrate - Google Patents
Forming method for monitoring circuit of semiconductor element formed on semiconductor substrateInfo
- Publication number
- JPS57193041A JPS57193041A JP7765081A JP7765081A JPS57193041A JP S57193041 A JPS57193041 A JP S57193041A JP 7765081 A JP7765081 A JP 7765081A JP 7765081 A JP7765081 A JP 7765081A JP S57193041 A JPS57193041 A JP S57193041A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- wiring layer
- monitoring
- psg
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To improve the yield of a method of forming a monitoring circuit by alloying electrodes of a monitoring element on an Si substrate and an initial wiring layer to monitor the propriety, thereby preventing a shortcircuit between layers produced due to a projection formed on the wiring layer. CONSTITUTION:A chip 12 of chips 11 on an Si substrate 10 is used as a monitor, and an initial wiring layer is adhered in the predetermined pattern, for example, to the electrodes of an MOSFET formed on the chip 12. Subsequently, in order to connect the electrodes to the wiring layer, a CO2 laser is emitted, is absorbed to an SiO2 and a PSG, the periphery of the electrodes is heated, a heat is transmitted to the Al and Si of the electrodes to alloy them. The Al and Si are alloyed optimally at 200-450 deg.C, whereupon no damage is produced at the insulating film. Thereafter, a probe is contacted with the electrodes of the monitoring element, the PSG is covered as the conventional manner when it is good, the second wiring layer of the prescribed pattern is formed, and the electrodes and the wiring layers for the element of a product except the monitoring element are alloyed by heating at the time of growing the PSG. According to this structure, the element of the chip of the product is not heated at the monitoring time, and can be monitored without shortcircuit due to the projections on the wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7765081A JPS57193041A (en) | 1981-05-22 | 1981-05-22 | Forming method for monitoring circuit of semiconductor element formed on semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7765081A JPS57193041A (en) | 1981-05-22 | 1981-05-22 | Forming method for monitoring circuit of semiconductor element formed on semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57193041A true JPS57193041A (en) | 1982-11-27 |
Family
ID=13639764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7765081A Pending JPS57193041A (en) | 1981-05-22 | 1981-05-22 | Forming method for monitoring circuit of semiconductor element formed on semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57193041A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4881029A (en) * | 1985-09-30 | 1989-11-14 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit devices and methods for testing same |
-
1981
- 1981-05-22 JP JP7765081A patent/JPS57193041A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4881029A (en) * | 1985-09-30 | 1989-11-14 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit devices and methods for testing same |
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