JPS57190364A - Manufacture of junction type fet - Google Patents
Manufacture of junction type fetInfo
- Publication number
- JPS57190364A JPS57190364A JP7493981A JP7493981A JPS57190364A JP S57190364 A JPS57190364 A JP S57190364A JP 7493981 A JP7493981 A JP 7493981A JP 7493981 A JP7493981 A JP 7493981A JP S57190364 A JPS57190364 A JP S57190364A
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- layer
- grown
- help
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract 1
- 230000002378 acidificating effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000007539 photo-oxidation reaction Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
PURPOSE:To produce a short gate FET by a method wherein, during the process of manufacturing an n channel J-FET, an n<+> type source and drain regions are diffusedly created in an n type semiconductor layer and the n type impurity containing oxide film grown on the entire surface in the process is replaced with an impurity free oxide film to be provided with a p<+> type gate region. CONSTITUTION:An n type layer 2 is epitaxially grown on a p type Si substrate 1. An SiO2 film 3 is formed to cover the layer 2 and openings 4a and 4b are prescribedly provided therein. n<+> type source and drain regions 5a and 5b are created by P diffusion into the layer 2 now transformed into islands. Next, only the P containing SiO2 film 6 grown on the film 3 is removed with help of an acidic ammonium fluoride or the like. Photo-oxidation exposes the film 3, which then is covered with another SiO2 film 12. A resist film 7 is applied to the film 12 and a hole 8 is provided therein between the regions 5a and 5b by photolithography. The exposed film 12 and then the film 3 is removed and a p<+> type gate region 10a is diffusedly formed in the layer 2 with help of B or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7493981A JPS57190364A (en) | 1981-05-20 | 1981-05-20 | Manufacture of junction type fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7493981A JPS57190364A (en) | 1981-05-20 | 1981-05-20 | Manufacture of junction type fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57190364A true JPS57190364A (en) | 1982-11-22 |
Family
ID=13561809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7493981A Pending JPS57190364A (en) | 1981-05-20 | 1981-05-20 | Manufacture of junction type fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57190364A (en) |
-
1981
- 1981-05-20 JP JP7493981A patent/JPS57190364A/en active Pending
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