JPS57184234A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57184234A
JPS57184234A JP6900881A JP6900881A JPS57184234A JP S57184234 A JPS57184234 A JP S57184234A JP 6900881 A JP6900881 A JP 6900881A JP 6900881 A JP6900881 A JP 6900881A JP S57184234 A JPS57184234 A JP S57184234A
Authority
JP
Japan
Prior art keywords
wiring
film
thickness
silicon
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6900881A
Other languages
Japanese (ja)
Inventor
Yukinobu Murao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6900881A priority Critical patent/JPS57184234A/en
Publication of JPS57184234A publication Critical patent/JPS57184234A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain wiring in which breaking at a stage section is not generated by coating a metallic film as a wiring material with silicon thinner than the thickness of the metallic film, reacting the metallic film and a silicon film through heat treatment and forming wiring. CONSTITUTION:An N<+> diffusion layer 102 is formed onto a P type Si substrate 100, a layer insulating film 104 is further shaped onto the layer 102, a contact hole 105 is formed to the insulating film, Al 106 as the metallic wiring material is coated through an evaporation method, the silicon 107 with the one fourth or more thickness of the thickness of the metallic film is coated through a plasma growth method, the surface is patterned, and Al and Si are reacted through heat treatment and the wiring is formed. Accordingly, the disconnecting section of Al is connected by the eutectoid of Al and Si, and disconnection is not generated at the stage section.
JP6900881A 1981-05-08 1981-05-08 Manufacture of semiconductor device Pending JPS57184234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6900881A JPS57184234A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6900881A JPS57184234A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184234A true JPS57184234A (en) 1982-11-12

Family

ID=13390132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6900881A Pending JPS57184234A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184234A (en)

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