JPS57184219A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57184219A
JPS57184219A JP6985981A JP6985981A JPS57184219A JP S57184219 A JPS57184219 A JP S57184219A JP 6985981 A JP6985981 A JP 6985981A JP 6985981 A JP6985981 A JP 6985981A JP S57184219 A JPS57184219 A JP S57184219A
Authority
JP
Japan
Prior art keywords
substrate
layer
contact window
shaped
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6985981A
Other languages
Japanese (ja)
Inventor
Kazunori Imaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6985981A priority Critical patent/JPS57184219A/en
Publication of JPS57184219A publication Critical patent/JPS57184219A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form the side surface of a contact window in gentle inclined plane- shaped form, and to prevent disconnection by shaping an electrode material layer or an insulator layer to the side surface of the contact window without being accompanied by treatment at a high temperature. CONSTITUTION:Field oxide films 24 are formed to the surface of a P<-> type Si substrate 21, the contact window section is shaped, an oxide film is molded onto the substrate 21 at the same time as a gate oxide film 26, and a PSG film 29 having the phosphorus of low concentration is further formed. The contact window 33 is shaped, an N<+> type region 31 formed at the same time as source- drain regions 30a, 30b is exposed, and a polycrystal Si layer 34 is molded through a CVD method. Polycrystal Si layers 34c coated to the side surfaces of the contact window 33 in inclined plane-shaped form are left and formed through the etching of the whole surface, and the Al electrode layer 36 is shaped onto the layers 34c. The Al layer 36 is sintered into the P<-> type Si substrate 21 while penetrating the N<+> type layer 31 through heating treatment, and a substrate electrode 36 connecting to the substrate 21 in ohmic shape is formed.
JP6985981A 1981-05-08 1981-05-08 Manufacture of semiconductor device Pending JPS57184219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6985981A JPS57184219A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6985981A JPS57184219A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184219A true JPS57184219A (en) 1982-11-12

Family

ID=13414948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6985981A Pending JPS57184219A (en) 1981-05-08 1981-05-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184219A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444474A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Contact forming method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444474A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Contact forming method of semiconductor device

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