JPS57167660A - Forming method for high-melting point metallic silicide layer - Google Patents

Forming method for high-melting point metallic silicide layer

Info

Publication number
JPS57167660A
JPS57167660A JP4710481A JP4710481A JPS57167660A JP S57167660 A JPS57167660 A JP S57167660A JP 4710481 A JP4710481 A JP 4710481A JP 4710481 A JP4710481 A JP 4710481A JP S57167660 A JPS57167660 A JP S57167660A
Authority
JP
Japan
Prior art keywords
layers
layer
melting point
onto
polycrystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4710481A
Other languages
Japanese (ja)
Other versions
JPS639661B2 (en
Inventor
Minoru Inoue
Yasuhisa Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4710481A priority Critical patent/JPS57167660A/en
Publication of JPS57167660A publication Critical patent/JPS57167660A/en
Publication of JPS639661B2 publication Critical patent/JPS639661B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form the excellent silicide layer having low resistance extending over the whole region by forming a polycrystal Si layer, to which phosphorus is doped, onto a base body to be treated, heating and annealing the base body, shaping a high-melting point metal layer onto the Si layer, elevating the temperature and alloying the Si layer and the metal layer. CONSTITUTION:Field oxide films 2 are formed to the surface of the first conduction type semiconductor substrate 1 and channel cut regions 3 under the films 2. A gate oxide film 4 is shaped onto the surface of the substrate 1, and a polycrystal Si layer 5 not doped is coated and molded. Phosphorus ions 6 are implanted in the whole upper surface of the layer 5, and the substrate 1 is heated and annealed in an inactive atmosphere and the polycrystal Si layers 5' to which phosphorus is doped are formed. The high-melting point metal layers 7 are shaped onto the layers 5', and gate wiring 8 with double structure consisting of the layers 5' and the layers 7 is formed onto the film 4 through selective etching. The whole is heated in an inactive atmosphere or vacuum, the layers 7 and the layers 5' are alloyed, and the gate wiring 9 of high-melting point metallic silicide is shaped.
JP4710481A 1981-03-30 1981-03-30 Forming method for high-melting point metallic silicide layer Granted JPS57167660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4710481A JPS57167660A (en) 1981-03-30 1981-03-30 Forming method for high-melting point metallic silicide layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4710481A JPS57167660A (en) 1981-03-30 1981-03-30 Forming method for high-melting point metallic silicide layer

Publications (2)

Publication Number Publication Date
JPS57167660A true JPS57167660A (en) 1982-10-15
JPS639661B2 JPS639661B2 (en) 1988-03-01

Family

ID=12765863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4710481A Granted JPS57167660A (en) 1981-03-30 1981-03-30 Forming method for high-melting point metallic silicide layer

Country Status (1)

Country Link
JP (1) JPS57167660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027517A (en) * 1988-06-27 1990-01-11 Sony Corp Manufacture of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7289194B2 (en) 2018-12-18 2023-06-09 住友化学株式会社 Method for producing porous layer, laminate, separator for non-aqueous electrolyte secondary battery, and non-aqueous electrolyte secondary battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333077A (en) * 1976-09-08 1978-03-28 Nec Corp Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333077A (en) * 1976-09-08 1978-03-28 Nec Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027517A (en) * 1988-06-27 1990-01-11 Sony Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS639661B2 (en) 1988-03-01

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