JPS57177542A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device

Info

Publication number
JPS57177542A
JPS57177542A JP6246281A JP6246281A JPS57177542A JP S57177542 A JPS57177542 A JP S57177542A JP 6246281 A JP6246281 A JP 6246281A JP 6246281 A JP6246281 A JP 6246281A JP S57177542 A JPS57177542 A JP S57177542A
Authority
JP
Japan
Prior art keywords
film
intrusion
si3n4
polycrystalline
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6246281A
Other languages
Japanese (ja)
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6246281A priority Critical patent/JPS57177542A/en
Publication of JPS57177542A publication Critical patent/JPS57177542A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To ensure high integration by a method wherein field oxide film intrusion is effectively suppressed through selective oxidation by using as a mask a lamination of a thin Si3N4 film and a thick protective film. CONSTITUTION:A p layer 6 is provided on the surface of an n type Si substrate 1 and piled successively thereon are an SiO2 thin film 7, an Si3N4 thin film 8, and a P added polycrystalline Si thick film 9. The lower limit of the Si3N4 film 8 is determined with the thickness of the polycrystalline Si film 9 set anywhere between 2,000 and 3,000Angstrom . With the film 8 thickness not less than 700Angstrom , bird's beak intrusion advances. The intrusion quantity is extremely small when an anti- oxidation masks 10 and 11 are produced by plasma etching and a field oxide film 12 by oxidation in moisture, and the films 9a and 9b change into PSG. When the films 9 and 8 are subjected to etching, the reacting speed of the film 9 is so great that the film 9 is completely etched away without affecting the oxide film 12. A gate oxide film 13 and a polycrystalline Si film 14 are successively laid for the completion of a CMOSFET on a single substrate by the conventional technique. Intrusion by a bird's beak is thereby reduced and high integration is ensured.
JP6246281A 1981-04-27 1981-04-27 Manufacturing method for semiconductor device Pending JPS57177542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6246281A JPS57177542A (en) 1981-04-27 1981-04-27 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6246281A JPS57177542A (en) 1981-04-27 1981-04-27 Manufacturing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS57177542A true JPS57177542A (en) 1982-11-01

Family

ID=13200893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6246281A Pending JPS57177542A (en) 1981-04-27 1981-04-27 Manufacturing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS57177542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008253962A (en) * 2007-04-09 2008-10-23 As One Corp Holding stand

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008253962A (en) * 2007-04-09 2008-10-23 As One Corp Holding stand

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