JPS57139953A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57139953A
JPS57139953A JP2582381A JP2582381A JPS57139953A JP S57139953 A JPS57139953 A JP S57139953A JP 2582381 A JP2582381 A JP 2582381A JP 2582381 A JP2582381 A JP 2582381A JP S57139953 A JPS57139953 A JP S57139953A
Authority
JP
Japan
Prior art keywords
stem
leads
guide
film carrier
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2582381A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6221267B2 (enExample
Inventor
Manabu Bonshihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2582381A priority Critical patent/JPS57139953A/ja
Publication of JPS57139953A publication Critical patent/JPS57139953A/ja
Publication of JPS6221267B2 publication Critical patent/JPS6221267B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP2582381A 1981-02-24 1981-02-24 Semiconductor device Granted JPS57139953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2582381A JPS57139953A (en) 1981-02-24 1981-02-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2582381A JPS57139953A (en) 1981-02-24 1981-02-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57139953A true JPS57139953A (en) 1982-08-30
JPS6221267B2 JPS6221267B2 (enExample) 1987-05-12

Family

ID=12176575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2582381A Granted JPS57139953A (en) 1981-02-24 1981-02-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57139953A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189742A (ja) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd ピングリツドアレイ
JPH03293739A (ja) * 1990-04-12 1991-12-25 Toshiba Corp 半導体装置
JPH08330464A (ja) * 1995-05-31 1996-12-13 Nec Kyushu Ltd ピン・グリッド・アレイ構造ｌｓｉ
JPH09191025A (ja) * 1995-05-08 1997-07-22 Fujitsu Ltd Ｉｃ支持フィルムの位置決め方法とそれを用いたｉｃチップの試験方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189742A (ja) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd ピングリツドアレイ
JPH03293739A (ja) * 1990-04-12 1991-12-25 Toshiba Corp 半導体装置
JPH09191025A (ja) * 1995-05-08 1997-07-22 Fujitsu Ltd Ｉｃ支持フィルムの位置決め方法とそれを用いたｉｃチップの試験方法
JPH08330464A (ja) * 1995-05-31 1996-12-13 Nec Kyushu Ltd ピン・グリッド・アレイ構造ｌｓｉ

Also Published As

Publication number Publication date
JPS6221267B2 (enExample) 1987-05-12

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