JPS57139941A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57139941A
JPS57139941A JP2649681A JP2649681A JPS57139941A JP S57139941 A JPS57139941 A JP S57139941A JP 2649681 A JP2649681 A JP 2649681A JP 2649681 A JP2649681 A JP 2649681A JP S57139941 A JPS57139941 A JP S57139941A
Authority
JP
Japan
Prior art keywords
film
wiring
etching
minute
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2649681A
Other languages
Japanese (ja)
Inventor
Masaharu Yorikane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2649681A priority Critical patent/JPS57139941A/en
Publication of JPS57139941A publication Critical patent/JPS57139941A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain excellent minute multilayer wiring by forming the first wiring to a minute clearance shaped by coating the first layer wiring metallic film and an insulating film on a substrate with a metal, which can be oxidized at an anode, through etching treatment and shaping the second wiring onto the first wiring through an insulating film. CONSTITUTION:The substrate 201 is coated with the SiO2 film 202 while excepting openings 203. The film 202 is coated successively with the first Al film 204, the first titanium film 205, the first Si3N4 film 206, the second Al film 207 and the second Si3N4 208. The film thickness is set to 0.5-1mum. The film 208 is etched using a resist 209 as a mask, and the surface is changed into oxidized Al 210 through the anode oxidation treatment of the second Al film 207 exposed. The first wiring is formed to the minute clearances 211 shaped by etching the film 208 in the lateral direction through gas etching through removal by etching extending over each film. The second wiring is formed onto the third Si3N4 film 212 shaped onto the first wiring. Accordingly, the minute multilayer wiring is stably formed.
JP2649681A 1981-02-25 1981-02-25 Manufacture of semiconductor device Pending JPS57139941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2649681A JPS57139941A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2649681A JPS57139941A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57139941A true JPS57139941A (en) 1982-08-30

Family

ID=12195092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2649681A Pending JPS57139941A (en) 1981-02-25 1981-02-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57139941A (en)

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