JPS57133657A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57133657A JPS57133657A JP2071481A JP2071481A JPS57133657A JP S57133657 A JPS57133657 A JP S57133657A JP 2071481 A JP2071481 A JP 2071481A JP 2071481 A JP2071481 A JP 2071481A JP S57133657 A JPS57133657 A JP S57133657A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- contact sections
- diffusion regions
- chip
- source line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000009792 diffusion process Methods 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 4
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To protect the device from surge breakdown, and to contract the size of a chip by forming metallic wiring, which shapes a Schottky barrier between itself and a substrate, between a diffusion region connected to an input/output pad and a diffusion region connected to a source line. CONSTITUTION:The input pad 1 and the source line 4 are each connected to the diffusion regions 2, 5 through contact sections 3, 6, and formed onto the Si substrate. The metallic wiring 15 consisting of a metal such as Al, to which the Schottky junction surface A is shaped, is formed onto the substrate between diffusion regions 8, 10 forming the contact sections. When high voltage is applied to the input pad 1, currents flowing between the diffusion regions 8, 10 can largely be decreased because an N<+> layer is not induced on the surface of the substrate between the contact sections 3, 6 and the resistance of the surface is increased. Consequently, the surge breakdown can be prevented, and the size of the chip can be contracted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2071481A JPS57133657A (en) | 1981-02-12 | 1981-02-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2071481A JPS57133657A (en) | 1981-02-12 | 1981-02-12 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57133657A true JPS57133657A (en) | 1982-08-18 |
Family
ID=12034817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2071481A Pending JPS57133657A (en) | 1981-02-12 | 1981-02-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57133657A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04343466A (en) * | 1991-05-21 | 1992-11-30 | Matsushita Electron Corp | Semiconductor integrated circuit device |
JP2021522692A (en) * | 2018-05-02 | 2021-08-30 | ウニヴェルシテ カトリック ド ルヴァンUniversite Catholique De Louvain | Integrated circuit devices and their manufacturing methods |
-
1981
- 1981-02-12 JP JP2071481A patent/JPS57133657A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04343466A (en) * | 1991-05-21 | 1992-11-30 | Matsushita Electron Corp | Semiconductor integrated circuit device |
JP2021522692A (en) * | 2018-05-02 | 2021-08-30 | ウニヴェルシテ カトリック ド ルヴァンUniversite Catholique De Louvain | Integrated circuit devices and their manufacturing methods |
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